NXP Semiconductors MC9S08LG16, Reference Manual

Page: 105 / 373

Chapter 6 Parallel Input/Output Control
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 105
6.7.2.3 Port B Pull Enable Register (PTBPE)
6.7.2.4 Port B Slew Rate Enable Register (PTBSE)
7 6 5 4 3 2 1 0
R
PTBPE7 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBPE2 PTBPE1 PTBPE0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-9. Internal Pull Enable for Port B Register (PTBPE)
Table 6-8. PTBPE Register Field Descriptions
Field Description
7:0
PTBPE[7:0]
Internal Pull Enable for Port B Bits — Each of these control bits determines if the internal pullup or pulldown
device is enabled for the associated PTB pin. For Port B pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pullup device disabled for Port B bit n.
1 Internal pullup device enabled for Port B bit n.
7 6 5 4 3 2 1 0
R
PTBSE7 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBSE2 PTBSE1 PTBSE0
W
Reset: 1 1 1 1 1 1 1 1
Figure 6-10. Slew Rate Enable for Port B Register (PTBSE)
Table 6-9. PTBSE Register Field Descriptions
Field Description
7:0
PTBSE[7:0]
Output Slew Rate Enable for Port B Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTB pin. For Port B pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for Port B bit n.
1 Output slew rate control enabled for Port B bit n.