NXP Semiconductors MC9S08LG16, Reference Manual

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MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 278
Chapter 14
Serial Peripheral Interface (S08SPIV4)
14.1 Introduction
The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication
between the MCU and peripheral devices. These peripheral devices can include other microcontrollers,
analog-to-digital converters, shift registers, sensors, memories, etc.
The SPI runs at a baud rate up to the bus clock divided by two in master mode and up to the bus clock
divided by 4 in slave mode. Software can poll the status flags, or SPI operation can be interrupt driven.
The SPI also supports a data length of 8 or 16 bits and includes a hardware match feature for the receive
data buffer.
Figure 14-1 shows the MC9S08LG32 series block diagram with the SPI block and pins highlighted.
14.1.1 Module Configuration
The SPI module pins, MISO, MOSI, SPSCK, and SS can be repositioned under software control using
MISO, MOSI, SCK, and SS bits in PINPS3 register as shown in
Table 14-1 . MISO, MOSI, SCK, and SS
bits in PINPS3 register selects which general-purpose I/O ports are associated with SPI operation.
14.1.2 SPI Clock Gating
The bus clock to the SPI can be gated on and off using the SPI bit in SCGC2. These bits are cleared after
any reset, which disables the bus clock to this module. To conserve power, these bits can be cleared to
disable the clock to this module when not in use. For more details, see
Section 5.7, “Peripheral Clock
Gating .”
Table 14-1. SPI Position Options
MISO/MOSI/SPSCK/SS Port Pin for MISO Port Pin for MOSI Port Pin for SPSCK Port Pin for SS
0 (default) PTF4 PTF5 PTF2 PTF3
1 PTI2 PTI3 PTI4 PTI5