NXP Semiconductors MC9S08LG16, Reference Manual

Page: 94 / 373

Chapter 5 Resets, Interrupts, and General System Control
MC9S08LG32 MCU Series, Rev. 5
94 Freescale Semiconductor
5.8.13 Pin Position Control Register (PINPS3)
This high-page register contains control bits that determine which of the two potential pins is used as the
source for the function. The default source is the pin available on the 48-pin package.
7 6 5 4 3 2 1 0
R
TX2 RX2 SCL SDA MISO MOSI SCK SS
W
Reset: 0 0 0 0 0 0 0 0
Figure 5-15. Pin Position Control Register (PINPS3)
Table 5-17. PINPS3 Register Field Descriptions
Field Description
7
TX2
TX2 Pin Position — This bit controls the pin position of TX2.
0 TX2 sourced from PTA3.
1 TX2 sourced from PTI1.
6
RX2
RX2 Pin Position — This bit controls the pin position of RX2.
0 RX2 sourced from PTA4.
1 RX2 sourced from PTI0.
5
SCL
SCL Pin Position — This bit controls the pin position of SCL.
0 SCL sourced from PTA1.
1 SCL sourced from PTI5.
4
SDA
SDA Pin Position — This bit controls the pin position of SDA.
0 SDA sourced from PTA2.
1 SDA sourced from PTI4.
3
MISO
MISO Pin Position — This bit controls the pin position of MISO.
0 MISO sourced from PTF4.
1 MISO sourced from PTI2.
2
MOSI
MOSI Pin Position — This bit controls the pin position of MOSI.
0 MOSI sourced from PTF5.
1 MOSI sourced from PTI3.
1
SCK
SCK Pin Position — This bit controls the pin position of SCK.
0 SCK sourced from PTF2.
1 SCK sourced from PTI4.
0
SS
SS Pin Position — This bit controls the pin position of SS.
0 SS sourced from PTF3.
1 SS sourced from PTI5.