NXP Semiconductors MC9S08LG16, Reference Manual

Page: 87 / 373

Chapter 5 Resets, Interrupts, and General System Control
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 87
5.8.7 System Power Management Status and Control 1 Register
(SPMSC1)
This high-page register contains status and control bits to support the low voltage detect function, and to
enable the bandgap voltage reference for use by the ADC module. To configure the low voltage detect trip
voltage, see
Table for the LVDV bit description in SPMSC2.
7 6 5 4 3 2 1 0
R LVWF
1
1
LVWF is set in the case when V
Supply
transitions below the trip point or after reset and V
Supply
is already below V
LVW
.
0
LVWIE LVDRE
2
2
Write-once only after any system reset
LVDSE LVDE
2
0
3
3
Bit 1 is a reserved bit that must always be written to 0.
BGBE
W LVWACK
RESET: 0 0 0 1 1 1 0 0
POR and LVD: 0 0 0 1 1 1 0 0
= Unimplemented or Reserved
Figure 5-9. System Power Management Status and Control 1 Register (SPMSC1)
Table 5-10. SPMSC1 Register Field Descriptions
Field Description
7
LVWF
Low-Voltage Warning Flag - The LVWF bit indicates the Low-Voltage Warning status.
0 Low voltage warning not present.
1 Low voltage warning is present or was present.
6
LVWACK
Low-Voltage Warning Acknowledge
The LVWACK bit indicates the Low-Voltage Warning Acknowledge status. Writing a logic 1 to LVWACK clears
LVWF to a logic 0 if a low voltage warning is not present.
5
LVWIE
Low-Voltage Warning Interrupt Enable
This bit enables hardware interrupt requests for LVWF..
0 Hardware interrupt disabled(use polling).
1 Request a hardware interrupt when LVWF=1.
4
VDRE
Low-Voltage Detect Reset Enable
This write-once bit enables LVD events to generate a hardware reset(provided LVDE=1). This bit has no effect if
the LVDE bit is a logic 0.
0 LVD events do not generate hardware resets.
1 Force an MCU reset when an enabled low-voltage detect event occurs.
3
LVDSE
Low-Voltage Detect Stop Enable
Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates when the
MCU is in stop mode. This bit has no effect if the LVDE bit is a logic 0.
0 Low-Voltage detect disabled during stop mode.
1 Low-Voltage detect enabled during stop mode.