NXP Semiconductors MC9S08LG16, Reference Manual

Page: 18 / 373

MC9S08LG32 MCU Series, Rev. 5
18 Freescale Semiconductor
Section Number Title Page
16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................316
16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................317
16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................318
16.4 Functional Description ...................................................................................................................319
16.4.1 Counter ............................................................................................................................320
16.4.2 Channel Mode Selection .................................................................................................321
16.5 Reset Overview ..............................................................................................................................324
16.5.1 General ............................................................................................................................324
16.5.2 Description of Reset Operation .......................................................................................324
16.6 Interrupts ........................................................................................................................................324
16.6.1 General ............................................................................................................................324
16.6.2 Description of Interrupt Operation .................................................................................325
Chapter 17
Modulo Timer (S08MTIMV1)
17.1 Introduction ....................................................................................................................................327
17.1.1 MTIM Clock Gating .......................................................................................................327
17.1.2 Features ...........................................................................................................................329
17.1.3 Modes of Operation ........................................................................................................329
17.1.4 Block Diagram ................................................................................................................330
17.2 External Signal Description ...........................................................................................................330
17.3 Memory Map and Register Definition ...........................................................................................331
17.3.1 Memory Map (Register Summary) .................................................................................331
17.3.2 Register Descriptions ......................................................................................................331
17.4 Functional Description ...................................................................................................................335
17.4.1 MTIM Operation Example .............................................................................................336
Chapter 18
Development Support
18.1 Introduction ....................................................................................................................................337
18.1.1 Forcing Active Background ............................................................................................337
18.1.2 Module Configuration .....................................................................................................337
18.1.3 Features ...........................................................................................................................338
18.2 Background Debug Controller (BDC) ...........................................................................................338
18.2.1 BKGD Pin Description ...................................................................................................339
18.2.2 Communication Details ..................................................................................................339
18.2.3 BDC Commands .............................................................................................................343
18.2.4 BDC Hardware Breakpoint .............................................................................................345
18.3 Register Definition .........................................................................................................................345
18.3.1 BDC Registers and Control Bits .....................................................................................346
18.3.2 System Background Debug Force Reset Register (SBDFR) ..........................................348