NXP Semiconductors MC9S08LG16, Reference Manual

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MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 241
Chapter 12
Inter-Integrated Circuit (S08IICV2)
12.1 Introduction
The inter-integrated circuit (IIC) provides a method of communication between a number of devices. The
interface is designed to operate up to 100 kbps with maximum bus loading and timing. The device is
capable of operating at higher baud rates, up to a maximum of clock/20, with reduced bus loading. The
maximum communication length and the number of devices that can be connected are limited by a
maximum bus capacitance of 400 pF.
NOTE
• MC9S08LG32 series of MCUs include only one IIC module, therefore
assume IICxA, IICxF, IICxC1, IICxS, IICxD, and IICxC2 register
definitions as IIC0A, IIC0F, IIC0C1, IIC0S, IIC0D, and IIC0C2.
• The SDA and SCL must not be driven above V
DD
. These pins are
pseudo open-drain and contain a protection diode to V
DD
.
12.1.1 Module Configuration
The IIC module pins, SDA and SCL can be repositioned under software control using SDA and SCL bits
in PINPS3 as shown in
Table 12-1 . SDA and SCL bits in PINPS3 selects which general-purpose I/O ports
are associated with IIC operation.
12.1.2 IIC Clock Gating
The bus clock to the IIC can be gated on and off using the IIC bit in SCGC1. This bit is cleared after any
reset, which disables the bus clock to this module. To conserve power, the IIC bit can be cleared to disable
the clock to this module when not in use. See
Section 5.7, “Peripheral Clock Gating ,” for details.
Table 12-1. IIC Position Options
SDA/SCL in PINPS3 Port Pin for SDA Port Pin for SCL
0 (default) PTA2 PTA1
1 PTI4 PTI5