NXP Semiconductors MC9S08LG16, Reference Manual

Page: 117 / 373

Chapter 6 Parallel Input/Output Control
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 117
6.7.6.3 Port F Pull Enable Register (PTFPE)
6.7.6.4 Port F Slew Rate Enable Register (PTFSE)
7 6 5 4 3 2 1 0
R
PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-29. Internal Pull Enable for Port F Register (PTFPE)
Table 6-28. PTFPE Register Field Descriptions
Field Description
7:0
PTFPE[7:0]
Internal Pull Enable for Port F Bits — Each of these control bits determines if the internal pullup or pulldown
device is enabled for the associated PTF pin. For Port F pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pullup device disabled for Port F bit n.
1 Internal pullup device enabled for Port F bit n.
7 6 5 4 3 2 1 0
R
PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
W
Reset: 1 1 1 1 1 1 1 1
Figure 6-30. Slew Rate Enable for Port F Register (PTFSE)
Table 6-29. PTFSE Register Field Descriptions
Field Description
7:0
PTFSE[7:0]
Output Slew Rate Enable for Port F Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTF pin. For Port F pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for Port F bit n.
1 Output slew rate control enabled for Port F bit n.