NXP Semiconductors MC9S08LG16, Reference Manual

Page: 10 / 373

MC9S08LG32 MCU Series, Rev. 5
10 Freescale Semiconductor
Section Number Title Page
4.2 MC9S08LG32 Series Memory Map ................................................................................................49
4.3 Reset and Interrupt Vector Assignments ..........................................................................................50
4.4 Register Addresses and Bit Assignments.........................................................................................52
4.4.1 Reserved Flash Locations .................................................................................................59
4.5 RAM.................................................................................................................................................60
4.6 Flash .................................................................................................................................................60
4.6.1 Features .............................................................................................................................61
4.6.2 Program and Erase Times .................................................................................................61
4.6.3 Program and Erase Command Execution .........................................................................62
4.6.4 Burst Program Execution ..................................................................................................63
4.6.5 Access Errors ....................................................................................................................65
4.6.6 Flash Block Protection ......................................................................................................65
4.6.7 Vector Redirection ............................................................................................................66
4.7 Security.............................................................................................................................................66
4.8 Flash Registers and Control Bits......................................................................................................67
4.8.1 Flash Clock Divider Register (FCDIV) ............................................................................68
4.8.2 Flash Options Register (FOPT and NVOPT) ....................................................................69
4.8.3 Flash Configuration Register (FCNFG) ...........................................................................70
4.8.4 Flash Protection Register (FPROT and NVPROT) ..........................................................70
4.8.5 Flash Status Register (FSTAT) ..........................................................................................71
4.8.6 Flash Command Register (FCMD) ...................................................................................72
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction ......................................................................................................................................73
5.2 Features ............................................................................................................................................73
5.3 MCU Reset.......................................................................................................................................73
5.4 Computer Operating Properly (COP) Watchdog..............................................................................74
5.5 Interrupts ..........................................................................................................................................75
5.5.1 Interrupt Stack Frame .......................................................................................................76
5.5.2 External Interrupt Request (IRQ) Pin ...............................................................................76
5.5.3 Interrupt Vectors, Sources, and Local Masks ...................................................................77
5.6 Low-Voltage Detect (LVD) System .................................................................................................79
5.6.1 Power-On Reset Operation ...............................................................................................79
5.6.2 Low-Voltage Detection (LVD) Reset Operation ...............................................................79
5.6.3 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................79
5.7 Peripheral Clock Gating ...................................................................................................................79
5.8 Reset, Interrupt, and System Control Registers and Control Bits....................................................80
5.8.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................80
5.8.2 System Reset Status Register (SRS) .................................................................................82
5.8.3 System Background Debug Force Reset Register (SBDFR) ............................................83
5.8.4 System Options Register 1 (SOPT1) ................................................................................84