NXP Semiconductors MC9S08LG16, Reference Manual

Page: 193 / 373

Chapter 8 LCD Module (S08LCDLPV1)
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 193
9.5.2.3
Initialization
Example 3
Example 3 LCD setup requirements are reiterated in the table below:
The table below lists the required setup values required to initialize the LCD as specified by Example 3:
LCDBPEN[5:0] LCDBPEN0
LCDBPEN1
LCDBPEN2
LCDBPEN3 00001111
00000000
00000000
00000000 Four backplane pins needed.
Note: Any enabled LCD pin can be enabled to operate as a backplane.
LCDWF[44:0] LCDWF0
LCDWF1
LCDWF2
LCDWF3 00000001
00000010
00000100
00001000 Configure which phase the four backplane pins will be active in. This
configuration sets LCD[0] to be active in Phase A, LCD[1] to be active in
Phase B etc.
Note: Any backplane pin can be active in any of the phases.
Example
Operating
Voltage,
V
DD
LCD Clock
Source
LCD Glass
Operating
Voltage
Required
LCD
segments
LCD
Frame
Rate
Blinking
Mode/Rate
Behavior in
STOP3 and
WAIT modes
LCD
Power
Input
3 5.0 V External
32.768 kHz
5 V 168 30 Hz Blank
2.0 Hz
WAIT: off
STOP: off
Power via
V
LL3
(RBias)
Table 9-25. Initialization Register Values for Example 3
Register
bit or
bit field
Binary
Value
Comment
LCDSUPPLY
0-00--11
CPSEL 0 Disable charge pump, Resistor network selected.
LADJ[1:0] 00 Configure LCD charge pump clock source
VSUPPLY[1:0] 11 When VSUPPLY[1:0] = 11, the LCD powered via V
LL3
(see Table 9-19 ).
LCDC1
0-----11
LCDIEN 0 LCD Frame Interrupts disabled
LCDWAI 1 LCD is “off” in WAIT mode
LCDSTP 1 LCD is “off” in STOP mode
LCDC0
00101111
LCDEN 0 Initialization is done before initializing the LCD module
SOURCE 0 Selects OSCOUT as the LCD clock source (32.768 kHz crystal)
LCLK[2:0] 101 For 1/8 duty cycle, select closest value to the desired 30 Hz LCD frame
frequency (see
Table 9-12 )
DUTY[2:0] 111 For 168 segments (8x21), select 1/8 duty cycle
Table 9-24. Initialization Register Values for Example 2 (continued)
Register
bit or
bit field
Binary
Value
Comment