NXP Semiconductors MC9S08LG16, Reference Manual

Page: 97 / 373

MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 97
Chapter 6
Parallel Input/Output Control
6.1 Introduction
This section explains software controls related to parallel input/output (I/O) and pin control. The
MC9S08LG32 has nine parallel I/O ports (PTA-PTI) which include a total of 69 I/O pins, including two
output-only pins. See
Chapter 2, “Pins and Connections ,” for more information about pin assignments and
external hardware considerations of these pins.
Many of these pins are shared with on-chip peripherals such as timer systems, communication systems, or
keyboard interrupts, as shown in
Table 2-1 . The peripheral modules have priority over the general-purpose
I/O functions so that when a peripheral is enabled, the I/O functions associated with the shared pins may
be disabled.
After reset, the shared peripheral functions are disabled and the pins are configured as inputs
(PTxDDn = 0). The pin control functions for each pin are configured as follows: slew rate control enabled
(PTxSEn = 1), low drive strength selected (PTxDSn = 0), and internal pullups disabled (PTxPEn = 0).
NOTE
All general-purpose I/O pins are not available on all packages. To avoid
extra current drain from floating input pins, your reset initialization routine
in the application program must either enable on-chip pullup devices or
change the direction of unconnected pins to outputs so the pins do not float.
6.2 Pins Shared with LCD
Pins that have shared function with the LCD have special behavior based on the state of the VSUPPLY
bits in the LCDSUPPLY register. These pins (PTA, PTB, PTC[4:0], PTD, PTE and PTG) can operate as
full complementary drive or open drain drive depending on the VSUPPLY bits. When V
LL3
is connected
to V
DD
externally, VSUPPLY = 11, FCDEN = 1, and RVEN = 0; the pins operate as full complementary
drive. For all other VSUPPLY modes, the GPIO shared with LCD operates as open drain.
6.3 Port Data and Data Direction
Reading and writing of parallel I/Os are performed through the port data registers (PTxDn). The direction,
either input or output, is controlled through the port data direction registers (PTxDDn). The parallel I/O
port function for an individual pin is illustrated in the block diagram shown in
Figure 6-1 .
The data direction control bit (PTxDDn) determines whether the output buffer or the input buffer for the
associated pin is enabled. When a shared digital function is enabled for a pin, the output buffer is controlled