NXP Semiconductors MC9S08LG16, Reference Manual

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Chapter 15 Modulo Timer (S08MTIMV1)
MC9S08LG32 MCU Series, Rev. 5
330 Freescale Semiconductor
17.1.4 Block Diagram
The block diagram for the modulo timer module is shown Figure 17-2 .
Figure 17-2. Modulo Timer (MTIM) Block Diagram
17.2 External Signal Description
The MTIM includes one external signal, TPMCLK, used to input an external clock when selected as the
MTIM clock source. The signal properties of TPMCLK are shown in
Table 17-1 .
The TPMCLK input must be synchronized by the bus clock. Also, variations in duty cycle and clock jitter
must be accommodated. Therefore, the TPMCLK signal must be limited to one-fourth of the bus
frequency.
The TPMCLK pin can be muxed with a general-purpose port pin. See the Chapter 2, “Pins and
Connections,” chapter for the pin location and priority of this function.
Table 17-1. External Signal Description
Signal Function I/O
TPMCLK External clock source input into MTIM I
BUSCLK
TPMCLK
SYNC
CLOCK
SOURCE
SELECT
PRESCALE
AND SELECT
DIVIDE BY
8-BIT COUNTER
(MTIMCNT)
8-BIT MODULO
(MTIMMOD)
8-BIT COMPARATOR
TRST
TSTP
CLKS
PS
XCLK
TOIE
MTIM
INTERRUPT
REQUEST
TOF