NXP Semiconductors MC9S08LG16, Reference Manual

Page: 114 / 373

Chapter 6 Parallel Input/Output Control
MC9S08LG32 MCU Series, Rev. 5
114 Freescale Semiconductor
6.7.5.3 Port E Pull Enable Register (PTEPE)
6.7.5.4 Port E Slew Rate Enable Register (PTESE)
7 6 5 4 3 2 1 0
R
PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-24. Internal Pull Enable for Port E Register (PTEPE)
Table 6-23. PTEPE Register Field Descriptions
Field Description
7:0
PTEPE[7:0]
Internal Pull Enable for Port E Bits — Each of these control bits determines if the internal pullup or pulldown
device is enabled for the associated PTE pin. For Port E pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pullup device disabled for Port E bit n.
1 Internal pullup device enabled for Port E bit n.
7 6 5 4 3 2 1 0
R
PTESE7 PTESE6 PTESE5 PTESE4 PTESE3 PTESE2 PTESE1 PTESE0
W
Reset: 1 1 1 1 1 1 1 1
Figure 6-25. Slew Rate Enable for Port E Register (PTESE)
Table 6-24. PTESE Register Field Descriptions
Field Description
7:0
PTESE[7:0]
Output Slew Rate Enable for Port E Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTE pin. For Port E pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for Port E bit n.
1 Output slew rate control enabled for Port E bit n.