NXP Semiconductors MC9S08LG16, Reference Manual

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Chapter 5 Resets, Interrupts, and General System Control
MC9S08LG32 MCU Series, Rev. 5
88 Freescale Semiconductor
5.8.8 System Power Management Status and Control 2 Register
(SPMSC2)
This register is used to report the status of the low voltage warning function, and to configure the stop
mode behavior of the MCU.
1 This bit can be written only one time after power-on reset. Additional writes are ignored.
2 This bit can be written only one time after reset. Additional writes are ignore.
2
LVDE
Low-Voltage Detect Enable
This write-once bit enables low-voltage detect logic and qualifies the operation of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
0
BGBE
Bandgap Buffer Enable
This bit enables an internal buffer for the bandgap voltage reference for use by the ADC module on one of its
internal channels.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.
7 6 5 4 3 2 1 0
R 0 0
LVDV
1
LVWV
PPDF 0 0
PPDC
2
W PPDACK
POR: 0 0 0 0 0 0 0 0
LVD: 0 0 U U 0 0 0 0
Any other Re-
set:
0 0 U U 0 0 0 0
= Unimplemented or Reserved U = Unaffected by MCU Reset
Figure 5-10. System Power Management Status and Control 2 Register (SPMSC2)
Table 5-11. SPMSC2 Register Field Descriptions
Field Description
5
LVDV
Low-Voltage Detect Voltage Select
This write-once bit selects the low voltage detect(LVD) trip point setting. It also selects warning voltage
range.See
Table 5-12 for definition of these voltages.
5
LVWV
Low-Voltage Warning Voltage Select
The bit selects the low voltage warning(LVW) trip point voltage. See Table 5-12 for definition of these voltages.
3
PPDF
Partial Power Down Flag
This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
Table 5-10. SPMSC1 Register Field Descriptions (continued)
Field Description