NXP Semiconductors MC9S08LG16, Reference Manual

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Chapter 6 Parallel Input/Output Control
MC9S08LG32 MCU Series, Rev. 5
108 Freescale Semiconductor
6.7.3.3 Port C Pull Enable Register (PTCPE)
6.7.3.4 Port C Slew Rate Enable Register (PTCSE)
7 6 5 4 3 2 1 0
R 0
PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCPE2 PTCPE1 PTCPE0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-14. Internal Pull Enable for Port C Register (PTCPE)
Table 6-13. PTCPE Register Field Descriptions
Field Description
6:0
PTCPE[6:0]
Internal Pull Enable for Port C Bits — Each of these control bits determines if the internal pullup or pulldown
device is enabled for the associated PTC pin. For Port C pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pullup device disabled for Port C bit n.
1 Internal pullup device enabled for Port C bit n.
7 6 5 4 3 2 1 0
R 0
PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0
W
Reset: 0 1 1 1 1 1 1 1
Figure 6-15. Slew Rate Enable for Port C Register (PTCSE)
Table 6-14. PTCSE Register Field Descriptions
Field Description
6:0
PTCSE[6:0]
Output Slew Rate Enable for Port C Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTC pin. For Port C pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for Port C bit n.
1 Output slew rate control enabled for Port C bit n.