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NXP Semiconductors MC9S08LG16, Reference Manual

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NXP Semiconductors MC9S08LG16 Reference Manual Download Page 263

 Chapter 11 Serial Communications Interface (S08SCIV4)

MC9S08LG32 MCU Series, Rev. 5

Freescale Semiconductor

263

 

Figure 13-3

 shows the receiver portion of the SCI.

Figure 13-3. SCI Receiver Block Diagram

H

8

7

6

5

4

3

2

1

0

L

SCID – Rx Buffer

(Read-Only)

Internal Bus

Stop

11-Bit Receive Shift Register

Start

Shift Direction

ls

b

From RxD Pin

Rate Clock

Rx Interrupt
Request

Data Recovery

Divide

16 ¥ Baud

Single-Wire

Loop Control

Wakeup

Logic

Al

l 1s

msb

From

Transmitter

Error Interrupt
Request

PARITY

CHECKING

By 16

RDRF

RIE

IDLE

ILIE

OR

ORIE

FE

FEIE

NF

NEIE

PF

LOOPS

PEIE

PT

PE

RSRC

WAKE

ILT

RWU

M

LBKDIF

LBKDIE

RXEDGIF

RXEDGIE

Active Edge

Detect

RXINV

LBKDE

RWUID

Summary of Contents for MC9S08LG16

Page 1: ...scale com MC9S08LG32RM Rev 5 8 2009 MC9S08LG32 MC9S08LG16 Reference Manual THIS DOCUMENT CONTAINS INFORMATION ON A NEW PRODUCT UNDER DEVELOPMENT FREESCALE RESERVES THE RIGHT TO CHANGE OR DISCONTINUE T...

Page 2: ......

Page 3: ...ng during in circuit debugging plus two more breakpoints in on chip debug module On chip in circuit emulator ICE debug module containing three comparators and nine trigger modes eight deep FIFO for st...

Page 4: ......

Page 5: ...on pinouts electricals characterization data and mechanical drawings Find the most current versions of all documents at http www freescale com MC9S08LG32RM Rev 5 8 2009 Freescale and the Freescale log...

Page 6: ...er Revision Date Description of Changes Rev 1 9 2008 First Initial Release Rev 2 9 2008 Second Initial Release Rev 3 11 2008 Alpha Customer Release Rev 4 2 2009 Launch Release Rev 5 8 2009 In Chapter...

Page 7: ...28 Chapter 8 Central Processor Unit S08CPUV5 135 Chapter 9 LCD Module S08LCDLPV1 158 Chapter 10 Analog to Digital Converter S08ADC12V1 200 Chapter 11 Internal Clock Source S08ICSV3 226 Chapter 12 Inte...

Page 8: ......

Page 9: ...ower 33 2 3 2 Oscillator 33 2 3 3 RESET 34 2 3 4 Background Mode Select BKGD MS 34 2 3 5 IRQ 35 2 3 6 LCD Pins 35 2 3 7 General Purpose I O GPIO and Peripheral Ports 36 Chapter 3 Modes of Operation 3...

Page 10: ...ion Register FPROT and NVPROT 70 4 8 5 Flash Status Register FSTAT 71 4 8 6 Flash Command Register FCMD 72 Chapter 5 Resets Interrupts and General System Control 5 1 Introduction 73 5 2 Features 73 5...

Page 11: ...lel Input Output Control 6 1 Introduction 97 6 2 Pins Shared with LCD 97 6 3 Port Data and Data Direction 97 6 4 Pullup Slew Rate and Drive Strength 98 6 4 1 Port Internal Pullup Enable 98 6 4 2 Port...

Page 12: ...2 2 Index Register H X 136 8 2 3 Stack Pointer SP 137 8 2 4 Program Counter PC 137 8 2 5 Condition Code Register CCR 137 8 3 Addressing Modes 139 8 3 1 Inherent Addressing Mode INH 139 8 3 2 Relative...

Page 13: ...s 0 5 BPEN0 BPEN5 169 9 3 9 LCD Waveform Registers LCDWF 44 0 170 9 4 Functional Description 174 9 4 1 LCD Driver Description 175 9 4 2 LCDWF Registers 183 9 4 3 LCD Display Modes 183 9 4 4 LCD Charge...

Page 14: ...APCTL2 212 10 3 10Pin Control 3 Register APCTL3 213 10 4 Functional Description 214 10 4 1 Clock Select and Divide Control 215 10 4 2 Input Select and Pin Control 215 10 4 3 Hardware Trigger 215 10 4...

Page 15: ...lock Gating 241 12 1 3 Features 243 12 1 4 Modes of Operation 243 12 1 5 Block Diagram 243 12 2 External Signal Description 244 12 2 1 SCL Serial Clock Line 244 12 2 2 SDA Serial Data Line 244 12 3 Re...

Page 16: ...Register SCIxD 271 13 3 Functional Description 271 13 3 1 Baud Rate Generation 271 13 3 2 Transmitter Functional Description 272 13 3 3 Receiver Functional Description 273 13 3 4 Interrupts and Status...

Page 17: ...ernal Signal Description 300 15 3 Register Definition 300 15 3 1 RTC Status and Control Register RTCSC 301 15 3 2 RTC Counter Register RTCCNT 302 15 3 3 RTC Modulo Register RTCMOD 302 15 4 Functional...

Page 18: ...27 17 1 1 MTIM Clock Gating 327 17 1 2 Features 329 17 1 3 Modes of Operation 329 17 1 4 Block Diagram 330 17 2 External Signal Description 330 17 3 Memory Map and Register Definition 331 17 3 1 Memor...

Page 19: ...n 351 19 1 3 Block Diagram 351 19 2 Signal Description 352 19 3 Memory Map and Registers 352 19 3 1 Module Memory Map 352 19 3 2 Register Descriptions 354 19 4 Functional Description 365 19 4 1 Compar...

Page 20: ......

Page 21: ...ing part numbers for different qualification tier products in Ordering Information section of MC9S08LG32 Data Sheet 1 1 Devices in the MC9S08LG32 Series Table 1 1 summarizes the feature set available...

Page 22: ...A RESET LIQUID CRYSTAL DISPLAY DRIVER ANALOG TO DIGITAL CONVERTER ADC 12 BIT AD 15 0 TPM2CH 5 0 TPMCLK TPMCLK LCD24 ADC1 TX2 KBI4 PTA3 LCD23 ADC0 SDA PTA2 LCD22 SCL PTA1 LCD21 PTA0 LG32 16K BYTES LG16...

Page 23: ...o Digital Converter ADC12 1 Central Processor Unit CPU 5 Inter Integrated Circuit IIC 2 Internal Clock Source ICS 3 Keyboard Interrupt KBI 2 Liquid Crystal Display Module LCD 1 Low Power Oscillator XO...

Page 24: ...r more information regarding the use of ICSERCLK with this module see Chapter 10 Analog to Digital Converter S08ADC12V1 ICSIRCLK This is an internal reference clock and can be selected as the RTC cloc...

Page 25: ...LK is a gated version of OSCOUT ICSERCLK is not available in STOP modes while OSCOUT is available if ERCLKEN and EREFSTEN are set Figure 1 2 System Clock Distribution Diagram TPM1 TPM2 SCI1 SCI2 BDC C...

Page 26: ...Chapter 1 Device Overview MC9S08LG32 MCU Series Rev 5 26 Freescale Semiconductor...

Page 27: ...ackage pins It includes pinout diagrams recommended system connections and detailed discussions of signals 2 2 Device Pin Assignment This section shows the pin assignments for MC9S08LG32 series The pr...

Page 28: ...TD0 LCD0 VCAP1 VCAP2 VLL1 VLL2 V LL3 PTF5 MOSI KBI2 TPM2CH3 PTF4 MISO KBI1 TPM2CH4 PTI5 TPM2CH0 SCL SS PTI4 TPM2CH1 SDA SPSCK PTI3 TPM2CH2 MOSI PTI2 TPM2CH3 MISO PTI1 TMRCLK TX2 PTI0 RX2 PTH7 KBI1 TPM...

Page 29: ...CD29 PTD1 LCD1 PTD0 LCD0 VCAP1 VCAP2 VLL1 VLL2 V LL3 PTF5 MOSI KBI2 TPM2CH3 PTF4 MISO KBI1 TPM2CH4 PTI5 TPM2CH0 SCL SS PTI4 TPM2CH1 SDA SPSCK PTH7 KBI1 TPM2CH4 V SS V DD PTF7 EXTAL PTF6 XTAL V DDA V R...

Page 30: ...18 19 37 38 39 13 24 25 36 48 9 10 11 VCAP1 12 VLL2 V SSA V REFL 20 PTF2 SPSCKS TPM1CH1 IRQ ADC14 21 PTF1 RX1 TPM1CH0 ADC13 22 23 PTC5 BKGD MS PTE6 LCD14 40 PTE5 LCD13 41 PTE4 LCD12 42 PTE3 LCD11 43...

Page 31: ...er 2 Pins and Connections MC9S08LG32 MCU Series Rev 5 Freescale Semiconductor 31 2 3 Recommended System Connections Figure 2 4 shows pin connections that are common to MC9S08LG32 series application sy...

Page 32: ...necessary for different LCD modes NOTE 3 NOTE 4 LCD Glass VLL1 VLL2 VCAP2 0 1 F 0 1 F 0 1 F VCAP1 0 1 F VLL3 LCD 44 0 LCD Module LCD28 ADC5 TPMCLK PTA7 LCD25 ADC2 RX2 KBI5 PTA4 PORT A LCD24 ADC1 TX2...

Page 33: ...the oscillator OSCOUT is used to run the RTC and LCD bypassing the ICS The oscillator can be configured to run in stop2 or stop3 modes For more information see Section 1 3 System Clock Distribution a...

Page 34: ...lly pulled up RESET pin when measured is below VDD The internal gates connected to this pin are pulled to VDD If the RESET pin is required to drive to a VDD level an external pullup must be used In EM...

Page 35: ...irrespective of whether or not this pin is configured as IRQ NOTE Care needs to be taken that if this pin is configured as input it is not low during stop2 mode otherwise the part exits stop2 mode ir...

Page 36: ...s a general purpose output or a peripheral uses the port pin as an output the software can select one of the two drive strengths and can enable or disable the slew rate control When a port pin is conf...

Page 37: ...PTF5 MOSI KBI2 TPM2CH3 23 19 15 PTF4 MISO KBI1 TPM2CH4 24 20 PTI5 TPM2CH0 SCL SS 25 21 PTI4 TPM2CH1 SDA SPSCK 26 PTI3 TPM2CH2 MOSI 27 PTI2 TPM2CH3 MISO 28 PTI1 TMRCLK TX2 29 PTI0 RX2 30 22 PTH7 KBI1...

Page 38: ...RX2 ADC2 LCD25 54 42 32 PTA3 KBI4 TX2 ADC1 LCD24 55 43 33 PTA2 SDA ADC0 LCD23 56 44 34 PTA1 SCL LCD22 57 45 PTG3 LCD36 58 46 PTG2 LCD35 59 47 35 PTA0 LCD21 60 48 36 PTC4 LCD20 61 49 37 PTC3 LCD19 62...

Page 39: ...ns MC9S08LG32 MCU Series Rev 5 Freescale Semiconductor 39 79 63 47 PTE1 LCD9 80 64 48 PTE0 LCD8 Table 2 1 Pin Availability by Package Pin Count continued Packages Lowest Priority Highest 80 64 48 Port...

Page 40: ...Chapter 2 Pins and Connections MC9S08LG32 MCU Series Rev 5 40 Freescale Semiconductor...

Page 41: ...ned and the I O states are held 3 3 Run Mode This is the normal operating mode for the MC9S08LG32 series In this mode the CPU executes code from internal memory with execution beginning at the address...

Page 42: ...e flash program memory before the MCU is operated in run mode for the first time When the MC9S08LG32 series is shipped from the Freescale Semiconductor factory the flash program memory is erased by de...

Page 43: ...he stop mode selection and the modes selected under various conditions The selected mode is entered following the execution of a STOP instruction 3 6 1 Stop2 Mode To enter stop2 execute a STOP instruc...

Page 44: ...ACK is written To maintain I O states for pins that were configured as GPIO before entering stop2 you restore the contents of the I O port registers to the port registers before writing to the PPDACK...

Page 45: ...the background debug mode all background commands are available 3 6 4 LVD Enabled in Stop Mode The LVD system can generate a reset or an interrupt when the supply voltage drops below the LVD or LVW t...

Page 46: ...is write accessible only through BDC commands 2 Configured within the ICS module based on the settings of IREFSTEN EREFSTEN IRCLKEN and ERCLKEN 3 In stop2 the CPU flash ICS and all peripheral modules...

Page 47: ...3 1 issue STOP instruction Stop2 Run assert zero on wakup pins PTC6 RESET or PTF2 IRQ 1 or RTC interrupt or POR 1 An analog connection from these pins to the on chip regulator wakes up the regulator...

Page 48: ...ptionally On1 1 Requires the asynchronous ADC clock For stop3 LVD must be enabled to run in stop if converting the bandgap channel BDM Off2 2 If ENBDM is set when entering stop2 the MCU will actually...

Page 49: ...nd other RAM and flash features 4 2 MC9S08LG32 Series Memory Map As shown in Figure 4 1 on chip memory in the MC9S08LG32 series of MCUs consists of RAM flash memory for nonvolatile data storage and I...

Page 50: ...vailable for user program MC9S08LG32 DIRECT PAGE REGISTERS RAM HIGH PAGE REGISTERS 1984 BYTES 0x1800 0x17FF 0xFFFF 16 384 BYTES UNIMPLEMENTED 0x7FFF 0x8000 0x005F 0x0060 0x187A 0x187B 0x081F 0x0820 MC...

Page 51: ...FFDF KBI Interrupt Vkeyboard 0xFFE0 0xFFE1 IIC Viic 0xFFE2 0xFFE3 SCI2 Transmit Vsci2tx 0xFFE4 0xFFE5 SCI2 Receive Vsci2rx 0xFFE6 0xFFE7 SCI2 Error Vsci2err 0xFFE8 0xFFE9 SPI Vspi 0xFFEA 0xFFEB LCD Fr...

Page 52: ...cause the nonvolatile register locations are flash memory they must be erased and programmed like other flash memory locations Direct page registers can be accessed with efficient direct addressing mo...

Page 53: ...RXEDGIE 0 SBR12 SBR11 SBR10 SBR9 SBR8 0x0011 SCI1BDL SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0x0012 SCI1C1 LOOPS SCISWAI RSRC M WAKE ILT PE PT 0x0013 SCI1C2 TIE TCIE RIE ILIE TE RE RWU SBK 0x0014 SCI1...

Page 54: ...ATE0 0x003D LCDS LCDIF 0 0 0 0 0 0 0 0x003E PTFD PTFD7 PTFD6 PTFD5 PTFD4 PTFD3 PTFD2 PTFD1 PTFD0 0x003F PTFDD PTFDD7 PTFDD6 PTFDD5 PTFDD4 PTFDD3 PTFDD2 PTFDD1 PTFDD0 0x0040 TPM1SC TOF TOIE CPWMS CLKSB...

Page 55: ...PEN39 PEN38 PEN37 PEN36 PEN35 PEN34 PEN33 PEN32 0x0825 LCDPEN5 PEN44 PEN43 PEN42 PEN41 PEN40 0x0826 0x0827 Reserved 0x0828 LCDBPEN0 BPEN7 BPEN6 BPEN5 BPEN4 BPEN3 BPEN2 BPEN1 BPEN0 0x0829 LCDBPEN1 BPEN...

Page 56: ...D24 BPALCD24 0x0849 LCDWF25 BPHLCD25 BPGLCD25 BPFLCD25 BPELCD25 BPDLCD25 BPCLCD25 BPBLCD25 BPALCD25 0x084A LCDWF26 BPHLCD26 BPGLCD26 BPFLCD26 BPELCD26 BPDLCD26 BPCLCD26 BPBLCD26 BPALCD26 0x084B LCDWF2...

Page 57: ...3 2 1 Bit 0 0x1812 DBGCBH Bit 15 14 13 12 11 10 9 Bit 8 0x1813 DBGCBL Bit 7 6 5 4 3 2 1 Bit 0 0x1814 DBGCCH Bit 15 14 13 12 11 10 9 Bit 8 0x1815 DBGCCL Bit 7 6 5 4 3 2 1 Bit 0 0x1816 DBGFH Bit 15 14...

Page 58: ...TDSE5 PTDSE4 PTDSE3 PTDSE2 PTDSE1 PTDSE0 0x184E PTDDS PTDDS7 PTDDS6 PTDDS5 PTDDS4 PTDDS3 PTDDS2 PTDDS1 PTDDS0 0x184F Reserved 0x1850 PTEPE PTEPE7 PTEPE6 PTEPE5 PTEPE4 PTEPE3 PTEPE2 PTEPE1 PTEPE0 0x185...

Page 59: ...y A security key cannot be entered directly through background debug commands This security key can be disabled completely by programming the KEYEN bit to 0 If the security key is disabled the only wa...

Page 60: ...t one past RAM TXS SP H X 1 When security is enabled the RAM is considered a secure memory resource and is not accessible through background debug mode BDM or through code executing from non secure me...

Page 61: ...an be written only once so normally this write is performed during reset initialization FCDIV cannot be written if the access error flag FACCERR in FSTAT is set Ensure that FACCERR is not set before w...

Page 62: ...ored in the flash 2 Write the command code for the desired command to FCMD The five valid commands are blank check 0x05 byte program 0x20 burst program 0x25 page erase 0x40 and mass erase 0x41 The com...

Page 63: ...ommand is issued the charge pump is enabled and then remains enabled after completion of the burst program operation if these two conditions are met The next burst program command has been queued befo...

Page 64: ...burst time This is because the high voltage to the array must be disabled and then enabled again If a new burst command has not been queued before the current command completes then the charge pump i...

Page 65: ...mand code 0x20 0x25 or 0x40 with a background debug command while the MCU is secured The background debug controller can only do blank check and mass erase commands when the MCU is secure Writing 0 to...

Page 66: ...r 0xFFFE FFFF is not For example if 512 bytes of flash are protected the protected address region is from 0xFE00 through 0xFFFF The interrupt vectors 0xFFC0 0xFFFD are redirected to the locations 0xFD...

Page 67: ...from outside the MCU system through a communication interface such as a serial I O 3 Writing 0 to KEYACC in the FCNFG register If the 8 byte key that was just written matches the key stored in the fla...

Page 68: ...mented or Reserved Figure 4 5 Flash Clock Divider Register FCDIV Table 4 7 FCDIV Register Field Descriptions Field Description 7 DIVLD Divisor Loaded Status Flag When set this read only status flag in...

Page 69: ...t is 0 the backdoor key mechanism cannot be used to disengage security The backdoor key mechanism is accessible only from the user secured firmware BDM commands cannot be used to write key comparison...

Page 70: ...nk check of flash SEC01 SEC00 Description 0 0 secure 0 1 secure 1 0 unsecured 1 1 secure 7 6 5 4 3 2 1 0 R 0 0 KEYACC 0 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 4 7 Flash Confi...

Page 71: ...that the command buffer is empty so that a new command sequence can be executed when performing burst programming The FCBEF bit is cleared by writing a 1 to it or when a burst program command is trans...

Page 72: ...ccess errors see Section 4 6 5 Access Errors FACCERR is cleared by writing a 1 to FACCERR Writing a 0 to FACCERR has no meaning or effect 0 No access error 1 An access error has occurred 2 FBLANK Flas...

Page 73: ...n set of initial conditions During reset most control and status registers are forced to initial values and the program counter is loaded from the reset vector 0xFFFE 0xFFFF On chip peripheral modules...

Page 74: ...the bus clock or an internal 1 kHz clock source With each clock source there is an associated short and long time out controlled by COPT in SOPT1 Table 5 1 summaries the control functions of the COPCL...

Page 75: ...d consists of Saving the CPU registers on the stack Setting the I bit in the CCR to mask further interrupts Fetching the interrupt vector for the highest priority interrupt that is currently pending F...

Page 76: ...red before returning from the ISR Typically the flag is cleared at the beginning of the ISR so that if another interrupt is generated by this same source it is registered so it can be serviced after c...

Page 77: ...interrupt request during IRQ initialization you must do the following 1 Mask IRQ interrupt by clearing IRQIE in IRQSC 2 Select the IRQ mode by writing to the IRQEDG IRQMOD and IRQPDD bits in IRQSC 3...

Page 78: ...FFE0 0xFFE1 Viic IIC IICIS IICIE IIC control 14 0xFFE2 0xFFE3 Vsci2tx SCI2 TDRE TC TIE TCIE SCI transmit 13 0xFFE4 0xFFE5 Vsci2rx SCI2 IDLE RDRF LBKDIF RXEDGIF ILIE RIE LBKDIE RXEDGIE SCI receive 12 0...

Page 79: ...the LVD system holds the MCU in reset until the supply voltage has risen above the low voltage detection threshold The LVD bit in the SRS register is set following either an LVD reset or POR 5 6 3 Low...

Page 80: ...ons are discussed in greater detail in Chapter 3 Modes of Operation 5 8 1 Interrupt Pin Request Status and Control Register IRQSC This direct page register includes status and control bits which are u...

Page 81: ...f edge and level detection is selected IRQMOD 1 IRQF cannot be cleared while the IRQ pin remains at its asserted level 1 IRQIE IRQ Interrupt Enable This read write control bit determines whether IRQ e...

Page 82: ...e cleared Note 2 Note 2 Note 2 0 0 0 Table 5 4 SRS Register Field Descriptions Field Description 7 POR Power On Reset Reset was caused by the power on detection logic Because the internal supply volta...

Page 83: ...bit is also set by POR 0 Reset not caused by LVD trip or POR 1 Reset caused by LVD trip or POR 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W BDFR1 1 BDFR is writable only through serial background debug comman...

Page 84: ...timer enabled force reset on timeout 6 COPT COP Watchdog Timeout This write once bit selects the timeout period of the COP COPT along with COPCLKS in SOPT2 defines the COP timeout period 0 Short time...

Page 85: ...n only one time after reset Additional writes are ignored 0 0 0 0 0 0 SPIFE W Reset 0 0 0 0 0 0 0 1 Unimplemented or Reserved Figure 5 6 System Options Register 2 SOPT2 Table 5 7 SOPT2 Register Field...

Page 86: ...SDIDH Register Field Descriptions Field Description 7 4 Reserved Bits 7 4 are reserved Reading these bits result in an indeterminate value writes have no effect 3 0 ID 11 8 Part Identification Number...

Page 87: ...VWF Low Voltage Warning Flag The LVWF bit indicates the Low Voltage Warning status 0 Low voltage warning not present 1 Low voltage warning is present or was present 6 LVWACK Low Voltage Warning Acknow...

Page 88: ...ts internal channels 0 Bandgap buffer disabled 1 Bandgap buffer enabled 7 6 5 4 3 2 1 0 R 0 0 LVDV1 LVWV PPDF 0 0 PPDC2 W PPDACK POR 0 0 0 0 0 0 0 0 LVD 0 0 U U 0 0 0 0 Any other Re set 0 0 U U 0 0 0...

Page 89: ...2 High LVD trip point VSUPPLY rising LVDV 1 4 00 4 20 V 3 Low LVD trip point VSUPPLY falling LVDV 0 VLVDXL 2 48 2 64 V 4 Low LVD trip point VSUPPLY rising LVDV 0 2 54 2 70 V 5 High LVW trip point VSU...

Page 90: ...TC module is enabled 6 TPM2 TPM2 Clock Gate Control This bit controls the clock gate to the TPM2 module 0 Bus clock to the TPM2 module is disabled 1 Bus clock to the TPM2 module is enabled 5 TPM1 TPM1...

Page 91: ...k Gate Control This bit controls the bus clock gate to the DBG module 0 Bus clock to the DBG module is disabled 1 Bus clock to the DBG module is enabled 6 FLS Flash Clock Gate Control This bit control...

Page 92: ...TA6 1 KBI7 sourced from PTH3 7 KBI6 KBI6 Pin Position This bit controls the pin position of KBI6 0 KBI6 sourced from PTA5 1 KBI6 sourced from PTH2 6 KBI5 KBI5 Pin Position This bit controls the pin po...

Page 93: ...6 6 TPM2 4 TPM2 4 Pin Position This bit controls the pin position of TPM2 4 0 TPM2 4 sourced from PTF4 1 TPM2 4 sourced from PTH7 5 TPM2 3 TPM2 3 Pin Position This bit controls the pin position of TPM...

Page 94: ...A3 1 TX2 sourced from PTI1 6 RX2 RX2 Pin Position This bit controls the pin position of RX2 0 RX2 sourced from PTA4 1 RX2 sourced from PTI0 5 SCL SCL Pin Position This bit controls the pin position of...

Page 95: ...the function The default source is the pin available on 48 pin package 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 TX1 RX1 W Reset 0 0 0 0 0 0 0 0 Figure 5 16 Pin Position Control Register PINPS4 Table 5 18 PINPS4...

Page 96: ...Chapter 5 Resets Interrupts and General System Control MC9S08LG32 MCU Series Rev 5 96 Freescale Semiconductor...

Page 97: ...not available on all packages To avoid extra current drain from floating input pins your reset initialization routine in the application program must either enable on chip pullup devices or change th...

Page 98: ...n momentarily with an old data value that happen to be in the port data register Figure 6 1 Parallel I O Block Diagram 6 4 Pullup Slew Rate and Drive Strength Associated with the parallel I O ports is...

Page 99: ...functions with the LCD operate as open drain outputs As an open drain output the output high of the pin is dependent upon the pullup resistor The pullup resistor can be an internal resistor enabled b...

Page 100: ...of the memory map The pullup slew rate and drive strength control registers are located in the high page section of the memory map Refer to tables in Chapter 4 Memory for the absolute address assignm...

Page 101: ...o all bits of this register For port A pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTAD to all 0s but these 0s are not driven out the corre...

Page 102: ...For port A pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup device disabled for port A bit n 1 Internal pullup device enabled...

Page 103: ...6 6 Drive Strength Selection for Port A Register PTADS Table 6 5 PTADS Register Field Descriptions Field Description 7 0 PTADS 7 0 Output Drive Strength Selection for Port A Bits Each of these control...

Page 104: ...ed as outputs reads return the last value written to this register Writes are latched into all bits of this register For Port B pins that are configured as outputs the logic level is driven out the co...

Page 105: ...For Port B pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup device disabled for Port B bit n 1 Internal pullup device enabled...

Page 106: ...11 Drive Strength Selection for Port B Register PTBDS Table 6 10 PTBDS Register Field Descriptions Field Description 7 0 PTBDS 7 0 Output Drive Strength Selection for Port B Bits Each of these contro...

Page 107: ...the pin For Port C pins that are configured as outputs reads return the last value written to this register Writes are latched into all bits of this register For Port C pins that are configured as ou...

Page 108: ...For Port C pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup device disabled for Port C bit n 1 Internal pullup device enabled...

Page 109: ...6 Drive Strength Selection for Port C Register PTCDS Table 6 15 PTCDS Register Field Descriptions Field Description 6 0 PTCDS 6 0 Output Drive Strength Selection for Port C Bits Each of these control...

Page 110: ...as outputs reads return the last value written to this register Writes are latched into all bits of this register For Port D pins that are configured as outputs the logic level is driven out the corre...

Page 111: ...For Port D pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup device disabled for Port D bit n 1 Internal pullup device enabled...

Page 112: ...21 Drive Strength Selection for Port D Register PTDDS Table 6 20 PTDDS Register Field Descriptions Field Description 7 0 PTDDS 7 0 Output Drive Strength Selection for Port D Bits Each of these contro...

Page 113: ...as outputs reads return the last value written to this register Writes are latched into all bits of this register For Port E pins that are configured as outputs the logic level is driven out the corre...

Page 114: ...For Port E pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup device disabled for Port E bit n 1 Internal pullup device enabled...

Page 115: ...26 Drive Strength Selection for Port E Register PTEDS Table 6 25 PTEDS Register Field Descriptions Field Description 7 0 PTEDS 7 0 Output Drive Strength Selection for Port E Bits Each of these contro...

Page 116: ...this register Writes are latched into all bits of this register For Port F pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTFD to all 0s but...

Page 117: ...For Port F pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup device disabled for Port F bit n 1 Internal pullup device enabled...

Page 118: ...31 Drive Strength Selection for Port F Register PTFDS Table 6 30 PTFDS Register Field Descriptions Field Description 7 0 PTFDS 7 0 Output Drive Strength Selection for Port F Bits Each of these contro...

Page 119: ...as outputs reads return the last value written to this register Writes are latched into all bits of this register For Port G pins that are configured as outputs the logic level is driven out the corre...

Page 120: ...For Port G pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup device disabled for Port G bit n 1 Internal pullup device enabled...

Page 121: ...36 Drive Strength Selection for Port G Register PTGDS Table 6 35 PTGDS Register Field Descriptions Field Description 7 0 PTGDS 7 0 Output Drive Strength Selection for Port G Bits Each of these contro...

Page 122: ...this register Writes are latched into all bits of this register For Port H pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTHD to all 0s but...

Page 123: ...For Port H pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup device disabled for Port H bit n 1 Internal pullup device enabled...

Page 124: ...41 Drive Strength Selection for Port H Register PTHDS Table 6 40 PTHDS Register Field Descriptions Field Description 7 0 PTHDS 7 0 Output Drive Strength Selection for Port H Bits Each of these contro...

Page 125: ...is register Writes are latched into all bits of this register For Port I pins that are configured as outputs the logic level is driven out the corresponding MCU pin Reset forces PTID to all 0s but the...

Page 126: ...For Port I pins that are configured as outputs these bits have no effect and the internal pull devices are disabled 0 Internal pullup device disabled for Port I bit n 1 Internal pullup device enabled...

Page 127: ...rive Strength Selection for Port I Register PTIDS Table 6 45 PTIDS Register Field Descriptions Field Description 7 0 PTIDS 7 0 Output Drive Strength Selection for Port I Bits Each of these control bit...

Page 128: ...ral purpose I O ports are associated with KBI operation 7 1 2 KBI Clock Gating The bus clock to the KBI can be gated on and off using the KBI bit in SCGC2 This bit is clear after any reset which disab...

Page 129: ...Y DRIVER ANALOG TO DIGITAL CONVERTER ADC 12 BIT AD 15 0 TPM2CH 5 0 TPMCLK TPMCLK LCD24 ADC1 TX2 KBI4 PTA3 LCD23 ADC0 SDA PTA2 LCD22 SCL PTA1 LCD21 PTA0 LG32 16K BYTES LG16 16K BYTES LCD26 ADC3 TPM2CH0...

Page 130: ...ction Therefore an enabled KBI pin KBPEx 1 can be used to bring the MCU out of wait mode if the KBI interrupt is enabled KBIE 1 7 1 4 2 KBI in Stop Modes The KBI operates asynchronously in stop3 mode...

Page 131: ...in enable register An 8 bit edge select register Refer to the direct page register summary in Chapter 4 Memory for the absolute address assignments for all KBI registers This section refers to registe...

Page 132: ...ted 2 KBACK Keyboard Acknowledge Writing a 1 to KBACK is part of the flag clearing mechanism KBACK always reads as 0 1 KBIE Keyboard Interrupt Enable KBIE determines whether a keyboard interrupt is re...

Page 133: ...he deasserted logic level A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 the deasserted level during one bus cycle and then a logic 0 the asserted level during t...

Page 134: ...Initialization When a keyboard interrupt pin is first enabled it is possible to get a false keyboard interrupt flag To prevent a false interrupt request during keyboard initialization the user must do...

Page 135: ...single 64 KB address space 16 bit stack pointer any size stack anywhere in 64 KB CPU address space 16 bit index register H X with powerful indexed addressing modes 8 bit accumulator A Many instruction...

Page 136: ...gisters H and X which often work together as a 16 bit address pointer where H holds the upper byte of an address and X holds the lower byte of the address All indexed addressing mode instructions use...

Page 137: ...M68HC05 Family and is seldom used in new HCS08 programs because it only affects the low order half of the stack pointer 8 2 4 Program Counter PC The program counter is a 16 bit register that contains...

Page 138: ...e interrupt service routine is executed Interrupts are not recognized at the instruction boundary after any instruction that clears I CLI or TAP This ensures that the next instruction after a CLI or T...

Page 139: ...are located within CPU registers so the CPU does not need to access memory to get any operands 8 3 2 Relative Addressing Mode REL Relative addressing mode is used to specify the destination location...

Page 140: ...ly used for MOV and CBEQ instructions 8 3 6 3 Indexed 8 Bit Offset IX1 This variation of indexed addressing uses the 16 bit value in the H X index register pair plus an unsigned 8 bit offset included...

Page 141: ...pin is no longer asserted At the conclusion of a reset event the CPU performs a 6 cycle sequence to fetch the reset vector from 0xFFFE and 0xFFFF and to fill the instruction queue in preparation for...

Page 142: ...CU through the background debug interface while the CPU is in wait mode CPU clocks will resume and the CPU will enter active background mode where other serial background commands can be processed Thi...

Page 143: ...er instructions and enter the active background mode The only way to resume execution of the user program is through reset or by a host debug system issuing a GO TRACE1 or TAGGO serial command through...

Page 144: ...nificant 8 bits X Index register lower order least significant 8 bits PC Program counter PCH Program counter higher order most significant 8 bits PCL Program counter lower order least significant 8 bi...

Page 145: ...plus signs are literal characters n Any label or expression that evaluates to a single integer in the range 0 7 opr8i Any label or expression that evaluates to an 8 bit immediate value opr16i Any lab...

Page 146: ...ion Address Mode Object Code Cycles Cyc by Cyc Details Affect on CCR V 1 1 H I N Z C ADC opr8i ADC opr8a ADC opr16a ADC oprx16 X ADC oprx8 X ADC X ADC oprx16 SP ADC oprx8 SP Add with Carry A A M C IMM...

Page 147: ...nch if Carry Bit Set if C 1 Same as BLO REL 25 rr 3 ppp 1 1 BEQ rel Branch if Equal if Z 1 REL 27 rr 3 ppp 1 1 BGE rel Branch if Greater Than or Equal To if N V 0 Signed REL 90 rr 3 ppp 1 1 BGND Enter...

Page 148: ...Not Equal if Z 0 REL 26 rr 3 ppp 1 1 BPL rel Branch if Plus if N 0 REL 2A rr 3 ppp 1 1 BRA rel Branch Always if I 1 REL 20 rr 3 ppp 1 1 BRCLR n opr8a rel Branch if Bit n in Memory Clear if Mn 0 DIR b0...

Page 149: ...3F 4F 5F 8C 6F 7F 9E 6F dd ff ff 5 1 1 1 5 4 6 rfwpp p p p rfwpp rfwp prfwpp 0 1 1 0 1 CMP opr8i CMP opr8a CMP opr16a CMP oprx16 X CMP oprx8 X CMP X CMP oprx16 SP CMP oprx8 SP Compare Accumulator wit...

Page 150: ...1 1 5 4 6 rfwpp p p rfwpp rfwp prfwpp 1 1 DIV Divide A H A X H Remainder INH 52 6 fffffp 1 1 EOR opr8i EOR opr8a EOR opr16a EOR oprx16 X EOR oprx8 X EOR X EOR oprx16 SP EOR oprx8 SP Exclusive OR Memor...

Page 151: ...Memory X M IMM DIR EXT IX2 IX1 IX SP2 SP1 AE BE CE DE EE FE 9E DE 9E EE ii dd hh ll ee ff ff ee ff ff 2 3 4 4 3 3 5 4 pp rpp prpp prpp rpp rfp pprpp prpp 0 1 1 LSL opr8a LSLA LSLX LSL oprx8 X LSL X L...

Page 152: ...to Stack Push A SP SP 0001 INH 87 2 sp 1 1 PSHH Push H Index Register High onto Stack Push H SP SP 0001 INH 8B 2 sp 1 1 PSHX Push X Index Register Low onto Stack Push X SP SP 0001 INH 89 2 sp 1 1 PULA...

Page 153: ...1 SEI Set Interrupt Mask Bit I 1 INH 9B 1 p 1 1 1 STA opr8a STA opr16a STA oprx16 X STA oprx8 X STA X STA oprx16 SP STA oprx8 SP Store Accumulator in Memory M A DIR EXT IX2 IX1 IX SP2 SP1 B7 C7 D7 E7...

Page 154: ...Byte PCL Interrupt Vector Low Byte INH 83 11 sssssvvfppp 1 1 1 TAP Transfer Accumulator to CCR CCR A INH 84 1 p 1 1 TAX Transfer Accumulator to X Index Register Low X A INH 97 1 p 1 1 TPA Transfer CCR...

Page 155: ...r 155 TXS Transfer Index Reg to SP SP H X 0001 INH 94 2 fp 1 1 WAIT Enable Interrupts Wait for Interrupt I bit 0 Halt CPU INH 8F 2 fp 1 1 0 Table 8 2 Instruction Set Summary Sheet 10 of 10 Source Form...

Page 156: ...RSET4 3 DIR 18 5 BSET4 2 DIR 28 3 BHCC 2 REL 38 5 LSL 2 DIR 48 1 LSLA 1 INH 58 1 LSLX 1 INH 68 5 LSL 2 IX1 78 4 LSL 1 IX 88 3 PULX 1 INH 98 1 CLC 1 INH A8 2 EOR 2 IMM B8 3 EOR 2 DIR C8 4 EOR 3 EXT D8...

Page 157: ...DEC 3 SP1 9EDA 5 ORA 4 SP2 9EEA 4 ORA 3 SP1 9E6B 8 DBNZ 4 SP1 9EDB 5 ADD 4 SP2 9EEB 4 ADD 3 SP1 9E6C 6 INC 3 SP1 9E6D 5 TST 3 SP1 9EAE 5 LDHX 2 IX 9EBE 6 LDHX 4 IX2 9ECE 5 LDHX 3 IX1 9EDE 5 LDX 4 SP2...

Page 158: ...nded For more details see AN3802 Interfacing LCD with MC9S08LG32 9 1 1 LCD Clock Sources The LCD module on MC9S08LG32 series can be clocked from the OSCOUT or the ICSIRCLK ALTCLK See Section 1 3 Syste...

Page 159: ...DRIVER ANALOG TO DIGITAL CONVERTER ADC 12 BIT AD 15 0 TPM2CH 5 0 TPMCLK TPMCLK LCD24 ADC1 TX2 KBI4 PTA3 LCD23 ADC0 SDA PTA2 LCD22 SCL PTA1 LCD21 PTA0 LG32 16K BYTES LG16 16K BYTES LCD26 ADC3 TPM2CH0...

Page 160: ...mode Blink operation in low power modes Programmable LCD power supply switch making it an ideal solution for battery powered and board level applications Charge pump requires only four external capaci...

Page 161: ...enabled to operate in stop2 The LCD frame interrupt does not cause the MCU to exit stop2 Stop3 Depending on the state of the LCDSTP bit the LCD module can operate an LCD panel in stop3 mode If LCDSTP...

Page 162: ...l Properties Name Port Function Reset State 45 LCD frontplane backplane LCD 44 0 Switchable frontplane backplane driver that connects directly to the display LCD 44 0 can operate as GPIO pins High imp...

Page 163: ...ate VLL1 and VLL2 Refer to VSUPPLY 1 0 bits explanation On 64 and 80 pin packages VLL3 and VLL3_2 pins provide the VLL3 supply to the LCD controller 9 2 3 Vcap1 Vcap2 The charge pump capacitor is used...

Page 164: ...to select which clock source is the basis for LCDCLK 0 Selects the OSCOUT external clock reference as the LCD clock source 1 Selects the alternate clock as the LCD clock source 5 3 LCLK 2 0 LCD Clock...

Page 165: ...r conditions necessary have been met The other conditions are VSUPPLY 11 and RVEN 0 0 GPIO shared with LCD operate as open drain outputs input levels and internal pullup resistors are referenced to VD...

Page 166: ...or the charge pump Higher loads require higher charge pump clock rates 00 Fastest clock source for charge pump LCD glass capacitance 8000pf or lower 01 Intermediate clock source for charge pump LCD gl...

Page 167: ...ignored if Duty is 5 or greater 0 Normal Display 1 Alternate display mode 5 BLANK Blank Display Mode Asserting this bit clears all segments in the LCD display 0 Normal or Alternate Display 1 Blank Dis...

Page 168: ...at perform word writes will lead to invalid data being placed in the register Initialize these registers before enabling the LCD module Exiting stop2 mode does not require reinitializing the LCDPEN re...

Page 169: ...Reset Indeterminate after reset LCDPEN1 R PEN15 PEN14 PEN13 PEN12 PEN11 PEN10 PEN9 PEN8 W Reset Indeterminate after reset LCDPEN2 R PEN23 PEN22 PEN21 PEN20 PEN19 PEN18 PEN17 PEN16 W Reset Indeterminat...

Page 170: ...0 W Reset Indeterminate after reset LCDBPEN1 R BPEN15 BPEN14 BPEN13 BPEN12 BPEN11 BPEN10 BPEN9 BPEN8 W Reset Indeterminate after reset LCDBPEN2 R BPEN23 BPEN22 BPEN21 BPEN20 BPEN19 BPEN18 BPEN17 BPEN1...

Page 171: ...CD5 BPCLCD5 BPBLCD5 BPALCD5 W Reset Indeterminate after reset LCDWF6 R BPHLCD6 BPGLCD6 BPFLCD6 BPELCD6 BPDLCD6 BPCLCD6 BPBLCD6 BPALCD6 W Reset Indeterminate after reset LCDWF7 R BPHLCD7 BPGLCD7 BPFLCD...

Page 172: ...ate after reset LCDWF19 R BPHLCD19 BPGLCD19 BPFLCD19 BPELCD19 BPDLCD19 BPCLCD19 BPBLCD19 BPALCD19 W Reset Indeterminate after reset LCDWF20 R BPHLCD20 BPGLCD20 BPFLCD20 BPELCD20 BPDLCD20 BPCLCD20 BPBL...

Page 173: ...D32 BPDLCD32 BPCLCD32 BPBLCD32 BPALCD32 W Reset Indeterminate after reset LCDWF33 R BPHLCD33 BPGLCD33 BPFLCD33 BPELCD33 BPDLCD33 BPCLCD33 BPBLCD33 BPALCD33 W Reset Indeterminate after reset LCDWF34 R...

Page 174: ...BPALCD42 W Reset Indeterminate after reset LCDWF43 R BPHLCD43 BPGLCD43 BPFLCD43 BPELCD43 BPDLCD43 BPCLCD43 BPBLCD43 BPALCD43 W Reset Indeterminate after reset LCDWF44 R BPHLCD44 BPGLCD44 BPFLCD44 BPE...

Page 175: ...even segment LCD display see Section 9 6 1 LCD Seven Segment Example Description 9 4 1 LCD Driver Description The LCD module driver has 8 modes of operation 1 1 duty 1 backplane Phase A 1 3 bias 4 vol...

Page 176: ...0 bit field in the LCDC0 register as shown in Table 9 11 9 4 1 2 LCD Bias Because a single frontplane driver is configured to drive more and more individual LCD segments 3 voltage levels are required...

Page 177: ...t the LCD display from flickering LCD module frame frequency is too low or ghosting LCD module frame frequency is too high To avoid these issues an LCD module frame frequency in the range of 28 to 58...

Page 178: ...4 32 32 34 1 32 34 1 28 4 36 6 32 5 28 4 28 4 30 3 28 4 30 3 25 3 32 5 28 4 6 25 6 25 6 27 3 25 6 27 3 22 8 29 3 25 6 7 23 3 23 3 24 8 23 3 24 8 20 7 26 6 23 3 Table 9 13 LCD Module Frame Frequency C...

Page 179: ...s BPEN0 1 and BPEN1 1 in the LCDBPEN0 LCD 0 assigned to Phase A LCDWF0 0x01 LCD 1 assigned to Phase B LCDWF1 0x02 Figure 9 13 1 2 Duty and 1 3 Bias Low Power Waveform LCD 0 BP0 BP0 FPn OFF LCD 1 BP1 L...

Page 180: ...assigned to Phase B LCDWF1 0x02 LCD 2 assigned to Phase C LCDWF2 0x04 LCD 3 assigned to Phase D LCDWF3 0x08 Figure 9 14 1 4 Duty and 1 3 Bias Low Power Waveform LCD 0 BP0 BP0 FPn ON 1 Frame LCD 1 BP1...

Page 181: ...DUTY 2 0 111 LCD pins 0 7 enabled as backplanes LCDBPEN0 0xFF LCD 0 assigned to Phase A LCDWF0 0x01 LCD 1 assigned to Phase B LCDWF1 0x02 LCD 2 assigned to Phase C LCDWF2 0x04 LCD 3 assigned to Phase...

Page 182: ...BP2 LCD 3 BP3 B D A C Phase F H E G B D A C Phase F H E G VLL1 VLL3 0 VLL2 VLL1 VLL3 0 VLL2 VLL1 VLL3 0 VLL2 VLL1 VLL3 0 VLL2 VLL1 VLL3 0 VLL2 VLL1 VLL3 0 VLL2 VLL3 VLL1 VLL2 VLL1 VLL3 0 VLL2 VLL3 VLL...

Page 183: ...ent on during the phase selected Writing a 0 to a given location results in the corresponding display segment being driven with the differential RMS voltage necessary to turn the segment off during th...

Page 184: ...etween display modes and blink modes If the LCD duty cycle is five backplanes or greater BMODE 1 is ignored and will revert to create a blank display during the blink period 9 4 3 2 Blink Frequency Th...

Page 185: ...s controlled by the VSUPPLY 1 0 bit field VSUPPLY 1 0 indicates the state of internal signals used to configure power switches as shown in the table in Figure 9 16 The block diagram in Figure 9 16 ill...

Page 186: ...ap1 and Vcap2 external pins are provided It is recommended that a ceramic capacitor be used Proper orientation is imperative when using a polarized capacitor The recommended value for the external cap...

Page 187: ...its above are not permissible LCD power supply modes and should be avoided Table 9 19 LCD Power Supply Options LCD Operational State LCD Power Supply Configuration VSUPPLY 1 0 CPSEL VLL3 is driven int...

Page 188: ...s During a reset the LCD module system is configured in the default mode The default mode includes the following settings VLL3 is driven externally for 3 V LCD Glass operation Resistor Bias Network en...

Page 189: ...section provides a recommended initialization sequence for the LCD module and also includes initialization examples for several LCD application scenarios 9 5 1 Initialization Sequence The below list p...

Page 190: ...requirements including Clock inputs sources LCD power supply LCD glass operating voltage LCD segment count Varied blink modes frequencies LCD frame rate 9 5 2 1 Initialization Example 1 Table 9 21 LCD...

Page 191: ...le select closest value to the desired 30 Hz LCD frame frequency see Table 9 12 DUTY 2 0 111 For 128 segments 8x16 select 1 8 duty cycle LCDBCTL 0XX XXXX BLINK 0 No blinking ALT X Alternate bit is con...

Page 192: ...clock source VSUPPLY 1 0 01 Generate VLL3 from VDD See Table 9 19 LCDC1 0 01 LCDIEN 0 LCD Frame Interrupts disabled LCDWAI 0 LCD is on in WAIT mode LCDSTP 1 LCD is off in STOP mode LCDC0 01010011 LCD...

Page 193: ...ed LCD segments LCD Frame Rate Blinking Mode Rate Behavior in STOP3 and WAIT modes LCD Power Input 3 5 0 V External 32 768 kHz 5 V 168 30 Hz Blank 2 0 Hz WAIT off STOP off Power via VLL3 RBias Table 9...

Page 194: ...Hz blink frequency using Table 9 17 LCDPEN 5 0 LCDPEN0 LCDPEN1 LCDPEN2 LCDPEN3 11111111 11111111 11111111 00011111 29 LCD pins need to be enabled LCDBPEN 5 0 LCDBPEN0 LCDBPEN1 LCDBPEN2 LCDBPEN3 11111...

Page 195: ...LCDIEN LCDIF Initialization Options LCDPENR 5 0 LCD Segment Energize ALT Data Bus LCD Segment Display and Blink Control LCDWF LCD Power Pins 0 1 F Vcap1 Vcap2 CTYP 0 1 F VLL3 VLL2 VLL1 LCD charge pum...

Page 196: ...acter 4 LCDWF0 XXXXX01X LCDWF1 XXXXX010 LCDWF2 XXXXXX11 FP0 e f COMMONED FP1 a d g COMMONED FP2 b c COMMONED a f e b c g d X don t care For this LCD Module any of the LCD pins can be configured to be...

Page 197: ...9 6 1 1 LCD Module Waveforms Figure 9 19 LCD Waveforms V3 V2 V1 V0 V3 V2 V1 V0 1FRAME LCD3 BP0 V3 V2 V0 V3 V1 V0 V3 V2 V1 V0 V1 V2 LCD4 BP1 LCD5 BP2 V3 V2 V1 V0 LCD0 FP0 LCD1 FP1 LCD2 FP2 BPBLCD0 BPC...

Page 198: ...ved when the LCD power supply is adjusted above and below the LCD threshold voltage The LCD threshold voltage is the nominal voltage required to energize the LCD segments For 3 V LCD glass the LCD thr...

Page 199: ...heir values upon stop2 recovery and do not need to be re written LCD GLASS PANEL LCD 10 4 LCD 3 0 LCD Power Pins 0 1 F Vcap1 Vcap2 CTYP 0 1 F VLL3 VLL2 VLL1 LCD charge pump capacitance LCD 10 4 LCD 3...

Page 200: ...ust be disabled for these pins to operate as ADC pins As ADC inputs these pins operate just like other ADC pins If the ADC channel input channel voltage is more that the LCD reference voltage VMCU or...

Page 201: ...VDDA VREFH XTAL EXTAL IRQ KBI 7 0 PORT A RESET LIQUID CRYSTAL DISPLAY DRIVER ANALOG TO DIGITAL CONVERTER ADC 12 BIT AD 15 0 TPM2CH 5 0 TPMCLK TPMCLK LCD24 ADC1 TX2 KBI4 PTA3 LCD23 ADC0 SDA PTA2 LCD22...

Page 202: ...DACK within the module or the alternate clock ALTCLK The Table 10 1 ADC Channel Assignment ADCH Channel Input Pin Control ADCH Channel Input Pin Control 00000 AD0 PTA2 ADP0 ADPC0 10000 AD16 Reserved N...

Page 203: ...4 5 Temperature Sensor The ADC module includes a temperature sensor whose output is connected to one of the ADC analog channel inputs Equation 10 1 provides an approximate transfer function of the te...

Page 204: ...omatic return to idle after single conversion Configurable sample time and conversion speed power Conversion complete flag and interrupt Input clock selectable from up to four sources Operation in wai...

Page 205: ...on AD27 AD0 Analog Channel inputs VREFH High reference voltage VREFL Low reference voltage VDDA Analog power supply VSSA Analog ground AD0 AD27 VREFH VREFL ADVIN ADCH Control Sequencer initialize samp...

Page 206: ...ternal source between the minimum VDDA spec and the VDDA potential VREFH must never exceed VDDA 10 2 4 Voltage Reference Low VREFL VREFL is the low reference voltage for the converter In some packages...

Page 207: ...SC1 when software triggered operation is selected or one conversion following assertion of ADHWT when hardware triggered operation is selected 1 Continuous conversions initiated following a write to A...

Page 208: ...1 Bits 1 and 0 are reserved bits that must always be written to 0 R1 W Reset 0 0 0 0 0 0 0 0 Figure 10 4 Status and Control Register 2 ADCSC2 Table 10 5 ADCSC2 Register Field Descriptions Field Descr...

Page 209: ...ad until the after next conversion is completed the intermediate conversion results are lost In 8 bit mode there is no interlocking with ADCRH If the MODE bits are changed any data in ADCRL becomes in...

Page 210: ...0 Figure 10 8 Compare Value Low Register ADCCVL 7 6 5 4 3 2 1 0 R ADLPC ADIV ADLSMP MODE ADICLK W Reset 0 0 0 0 0 0 0 0 Figure 10 9 Configuration Register ADCCFG Table 10 6 ADCCFG Register Field Desc...

Page 211: ...source to generate the internal clock ADCK See Table 10 9 Table 10 7 Clock Divide Select ADIV Divide Ratio Clock Rate 00 1 Input clock 01 2 Input clock 2 10 4 Input clock 4 11 8 Input clock 8 Table 1...

Page 212: ...O control disabled 4 ADPC4 ADC Pin Control 4 ADPC4 controls the pin associated with channel AD4 0 AD4 pin I O control enabled 1 AD4 pin I O control disabled 3 ADPC3 ADC Pin Control 3 ADPC3 controls t...

Page 213: ...O control disabled 4 ADPC12 ADC Pin Control 12 ADPC12 controls the pin associated with channel AD12 0 AD12 pin I O control enabled 1 AD12 pin I O control disabled 3 ADPC11 ADC Pin Control 11 ADPC11 c...

Page 214: ...sion with the contents of its compare registers The compare function is enabled by setting the ACFE bit and operates with any of the conversion modes and configurations Table 10 12 APCTL3 Register Fie...

Page 215: ...cy This divider is specified by the ADIV bits and can be divide by 1 2 4 or 8 10 4 2 Input Select and Pin Control The pin control registers APCTL3 APCTL2 and APCTL1 disable the I O port control of the...

Page 216: ...ed if AIEN is high at the time that COCO is set A blocking mechanism prevents a new result from overwriting previous data in ADCRH and ADCRL if the previous data is in the process of being read while...

Page 217: ...value of the analog signal The result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion algorithm If the bus frequency is less than the fADCK frequency precise sam...

Page 218: ...the compare value is transferred to ADCRH and ADCRL Upon completion of a conversion while the compare function is enabled if the compare condition is not true COCO is not set and no data is transferr...

Page 219: ...g stop3 mode For guaranteed ADC operation the MCU s voltage regulator must remain active during stop3 mode Consult the module introduction for configuration information for this MCU If a conversion is...

Page 220: ...ion 2 Update status and control register 2 ADCSC2 to select the conversion trigger hardware or software and compare function options if enabled 3 Update status and control register 1 ADCSC1 to select...

Page 221: ...channel ADCRH L 0xxx Holds results of conversion Read high byte ADCRH before low byte ADCRL so that conversion data cannot be overwritten with data from the next conversion ADCCVH L 0xxx Holds compar...

Page 222: ...e ground connection between these supplies must be at the VSSA pin This should be the only ground connection between these supplies if possible The VSSA pin makes a good single point ground location 1...

Page 223: ...3FF full scale 10 bit representation or 0xFF full scale 8 bit representation If the input is equal to or less than VREFL the converter circuit converts it to 0x000 Input voltages between VREFH and VRE...

Page 224: ...annot be placed in wait or stop3 or I O activity cannot be halted these recommended actions may reduce the effect of noise on the accuracy Place a 0 01 F capacitor CAS on the selected input channel to...

Page 225: ...bsolute value of the running sum of DNL achieves More simply this is the worst case difference of the actual transition voltage to a given code and its corresponding ideal transition voltage for all c...

Page 226: ...ICSOUT it is passed through a reduced bus divider BDIV which allows a lower final output clock frequency to be derived NOTE The ICS on the MC9S08LG32 series is configured to support only the low and m...

Page 227: ...LAY DRIVER ANALOG TO DIGITAL CONVERTER ADC 12 BIT AD 15 0 TPM2CH 5 0 TPMCLK TPMCLK LCD24 ADC1 TX2 KBI4 PTA3 LCD23 ADC0 SDA PTA2 LCD22 SCL PTA1 LCD21 PTA0 LG32 16K BYTES LG16 16K BYTES LCD26 ADC3 TPM2C...

Page 228: ...ichever clock is selected as the source can be divided down 2 bit select for clock divider is provided Allowable dividers are 1 2 4 8 Control signals for a low power oscillator clock generator OSCOUT...

Page 229: ...ed external mode the ICS supplies a clock derived from the FLL which is controlled by an external reference clock source The BDC clock is supplied from the FLL 11 1 3 3 FLL Bypassed Internal FBI In FL...

Page 230: ...nd the ICS supplies a clock derived from the external reference clock The BDC clock is not available 11 1 3 7 Stop STOP In stop mode the FLL is disabled and the internal reference clock ICSIRCLK and X...

Page 231: ...the external reference clock Resulting frequency must be in the range 31 25 kHz to 39 0625 kHz See Table 11 3 for the divide by factors 2 IREFS Internal Reference Select The IREFS bit selects the ref...

Page 232: ...Chapter 16 Internal Clock Source S08ICSV3 MC9S08LG32 MCU Series Rev 5 232 Freescale Semiconductor 6 64 Reserved 7 128 Reserved 1 Reset default Table 11 3 Reference Divide Factor RDIV RANGE 0 RANGE 1...

Page 233: ...oscillator mode of operation 1 Configure external oscillator for high gain operation 0 Configure external oscillator for low power operation 3 LP Low Power Select The LP bit controls whether the FLL i...

Page 234: ...DRS DCO Range Status The DRST read field indicates the current frequency range for the FLL output DCOOUT See Table 11 7 The DRST field does not update immediately after a write to the DRS field due t...

Page 235: ...rnal oscillator clock have completed This bit is only cleared when either ERCLKEN or EREFS are cleared 0 FTRIM ICS Fine Trim The FTRIM bit controls the smallest adjustment of the internal reference cl...

Page 236: ...ock is derived from the FLL clock which is controlled by the internal reference clock The FLL loop will lock the frequency to the FLL factor times the internal reference frequency The ICSLCLK is avail...

Page 237: ...LL bypassed internal mode the ICSOUT clock is derived from the internal reference clock The FLL clock is controlled by the internal reference clock and the FLL loop will lock the FLL frequency to the...

Page 238: ...gnals are static except in the following cases ICSIRCLK will be active in stop mode when all the following conditions occur IRCLKEN bit is written to 1 IREFSTEN bit is written to 1 OSCOUT will be acti...

Page 239: ...source The ICSIRCLK frequency can be re targeted by trimming the period of the internal reference clock This can be done by writing a new value to the TRIM bits in the ICSTRM register Writing a large...

Page 240: ...1 the external reference clock source OSCOUT will keep running during stop mode in order to provide a fast recovery upon exiting stop 11 4 8 Fixed Frequency Clock The ICS presents the divided FLL ref...

Page 241: ...initions as IIC0A IIC0F IIC0C1 IIC0S IIC0D and IIC0C2 The SDA and SCL must not be driven above VDD These pins are pseudo open drain and contain a protection diode to VDD 12 1 1 Module Configuration Th...

Page 242: ...SPLAY DRIVER ANALOG TO DIGITAL CONVERTER ADC 12 BIT AD 15 0 TPM2CH 5 0 TPMCLK TPMCLK LCD24 ADC1 TX2 KBI4 PTA3 LCD23 ADC0 SDA PTA2 LCD22 SCL PTA1 LCD21 PTA0 LG32 16K BYTES LG16 16K BYTES LCD26 ADC3 TPM...

Page 243: ...top signal generation detection Repeated start signal generation Acknowledge bit generation detection Bus busy detection General call recognition 10 bit address extension 12 1 4 Modes of Operation A b...

Page 244: ...e bidirectional SDA is the serial data line of the IIC system 12 3 Register Definition This section consists of the IIC register descriptions in address order Refer to the direct page register summary...

Page 245: ...F 7 6 5 4 3 2 1 0 R AD7 AD6 AD5 AD4 AD3 AD2 AD1 0 W Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 12 3 IIC Address Register IICxA Table 12 2 IICxA Field Descriptions Field Description 7 1 AD...

Page 246: ...12 5 provides the SCL divider and hold values for corresponding values of the ICR The SCL divider multiplied by multiplier factor mul generates IIC baud rate Eqn 12 1 SDA hold time is the delay from...

Page 247: ...29 384 33 190 193 0A 36 9 14 19 2A 448 65 222 225 0B 40 9 16 21 2B 512 65 254 257 0C 44 11 18 23 2C 576 97 286 289 0D 48 11 20 25 2D 640 97 318 321 0E 56 13 24 29 2E 768 129 382 385 0F 68 13 30 35 2F...

Page 248: ...ode of operation changes from master to slave 0 Slave mode 1 Master mode 4 TX Transmit Mode Select The TX bit selects the direction of master and slave transfers In master mode this bit should be set...

Page 249: ...hen a stop signal is detected 0 Bus is idle 1 Bus is busy 4 ARBL Arbitration Lost This bit is set by hardware when the arbitration procedure is lost The ARBL bit must be cleared by software by writing...

Page 250: ...o IICxD following assertion of MST is used for the address transfer and should comprise of the calling address in bit 7 to bit 1 concatenated with the required R W bit in position bit 0 12 3 6 IIC Con...

Page 251: ...owing sections and illustrated in Figure 12 9 Figure 12 9 IIC Bus Transmission Signals 12 4 1 1 Start Signal When the bus is free no master device is engaging the bus SCL and SDA lines are at logical...

Page 252: ...dress information for the slave device Each data byte is 8 bits long Data may be changed only while SCL is low and must be held stable while SCL is high as shown in Figure 12 9 There is one clock puls...

Page 253: ...ving SDA output In this case the transition from master to slave mode does not generate a stop condition Meanwhile a status bit is set by hardware to indicate loss of arbitration 12 4 1 7 Clock Synchr...

Page 254: ...A1 Then each slave that finds a match compares the eight bits of the second byte of the slave address with its own address Only one slave finds a match and generates an acknowledge A2 The matching sl...

Page 255: ...neral call If the value is 00 the match is a general call If the GCAEN bit is clear the IIC ignores any data supplied from a general call address by not issuing an acknowledgement 12 5 Resets The IIC...

Page 256: ...it If two or more masters try to control the bus at the same time the relative priority of the contending masters is determined by a data arbitration procedure The IIC module asserts this interrupt w...

Page 257: ...odule Initialization Master 1 Write IICF to set the IIC baud rate example provided in this chapter 2 Write IICC1 to enable IIC and interrupts 3 Initialize RAM variables IICEN 1 and IICIE 1 for transmi...

Page 258: ...CD ACK from Receiver Tx Next Byte Read Data from IICD and Store Switch to Rx Mode Dummy Read from IICD RTI Y N Y Y Y Y Y Y Y Y Y N N N N N N N N N Y TX RX RX TX Write Read N IICIF Address Transfer Dat...

Page 259: ...re control using TX1 RX1 TX2 and RX2 bits in PINPS4 and PINPS3 as shown in Table 13 1 TX1 RX1 TX2 and RX2 bits in PINPS4 and PINPS3 selects which general purpose I O ports are associated with IIC oper...

Page 260: ...DISPLAY DRIVER ANALOG TO DIGITAL CONVERTER ADC 12 BIT AD 15 0 TPM2CH 5 0 TPMCLK TPMCLK LCD24 ADC1 TX2 KBI4 PTA3 LCD23 ADC0 SDA PTA2 LCD22 SCL PTA1 LCD21 PTA0 LG32 16K BYTES LG16 16K BYTES LCD26 ADC3...

Page 261: ...plete Receive data register full Receive overrun parity error framing error and noise error Idle receiver detect Active edge on receive pin Break detect supporting LIN Hardware parity generation and c...

Page 262: ...iagram H 8 7 6 5 4 3 2 1 0 L SCID Tx Buffer Write Only Internal Bus Stop 11 bit Transmit Shift Register Start Shift Direction lsb 1 Baud Rate Clock Parity Generation Transmit Control Shift Enable Prea...

Page 263: ...Buffer Read Only Internal Bus Stop 11 Bit Receive Shift Register Start Shift Direction lsb From RxD Pin Rate Clock Rx Interrupt Request Data Recovery Divide 16 Baud Single Wire Loop Control Wakeup Log...

Page 264: ...il SCIxBDL is written SCIxBDL is reset to a non zero value so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled RE or TE bits in SCIxC2 a...

Page 265: ...and normal 2 pin full duplex modes When LOOPS is set the transmitter output is internally connected to the receiver input 0 Normal operation RxD and TxD use separate pins 1 Loop mode or single wire mo...

Page 266: ...or checking 1 Parity enabled 0 PT Parity Type Provided parity is enabled PE 1 this bit selects even or odd parity Odd parity means the total number of 1s in the data character including the parity bi...

Page 267: ...general purpose I O pin even if RE is set 0 Receiver off 1 Receiver on 1 RWU Receiver Wakeup Control This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automa...

Page 268: ...ve character is all 1s these bit times and the stop bit time count toward the full character time of logic high 10 or 11 bit times depending on the M control bit needed for the receiver to detect an i...

Page 269: ...ect circuitry is enabled and a LIN break character is detected LBKDIF is cleared by writing a 1 to it 0 No LIN break character has been detected 1 LIN break character has been detected 6 RXEDGIF RxD P...

Page 270: ...bit 1 SCI receiver active RxD input not idle 1 Setting RXINV inverts the RxD input for all cases data bits start and stop bits break and idle 7 6 5 4 3 2 1 0 R R8 T8 TXDIR TXINV ORIE NEIE FEIE PEIE W...

Page 271: ...k 4 TXINV1 Transmit Data Inversion Setting this bit reverses the polarity of the transmitted data output 0 Transmit data not inverted 1 Transmit data inverted 3 ORIE Overrun Interrupt Enable This bit...

Page 272: ...re 13 2 The transmitter output TxD idle state defaults to logic high TXINV is cleared following reset The transmitter output is inverted by setting TXINV The transmitter is enabled by setting the TE b...

Page 273: ...be sent as soon as the shifter is available As long as the character in the shifter does not finish while TE is cleared the SCI transmitter never actually releases control of the TxD pin If there is...

Page 274: ...least two of the samples at RT3 RT5 and RT7 are 0 even if one or all of the samples taken at RT8 RT9 and RT10 are 1s If any sample in any bit time including the start and stop bits in a character fram...

Page 275: ...matically when the receiver detects a logic 1 in the most significant bit of a received character eighth bit when M is cleared and ninth bit when M is set Address mark wakeup allows messages to contai...

Page 276: ...already set when a new character is ready to be transferred from the receive shifter to the receive data buffer the overrun OR flag is set instead of the data along with any associated NF FE or PF con...

Page 277: ...eck software independent of connections in the external system to help isolate system problems In this mode the transmitter output is internally connected to the receiver input and the RxD pin is not...

Page 278: ...Figure 14 1 shows the MC9S08LG32 series block diagram with the SPI block and pins highlighted 14 1 1 Module Configuration The SPI module pins MISO MOSI SPSCK and SS can be repositioned under software...

Page 279: ...ISPLAY DRIVER ANALOG TO DIGITAL CONVERTER ADC 12 BIT AD 15 0 TPM2CH 5 0 TPMCLK TPMCLK LCD24 ADC1 TX2 KBI4 PTA3 LCD23 ADC0 SDA PTA2 LCD22 SCL PTA1 LCD21 PTA0 LG32 16K BYTES LG16 16K BYTES LCD26 ADC3 TP...

Page 280: ...System Block Diagram Figure 14 2 shows the SPI modules of two MCUs connected in a master slave arrangement The master device initiates all SPI data transfers During a transfer the master shifts data...

Page 281: ...tten to the double buffered transmitter write to SPIxD and gets transferred to the SPI shift register at the start of a data transfer After shifting in a byte of data the data is transferred into the...

Page 282: ...SPR3 SPR2 SPR1 SPR0 divide the output of the prescaler stage by 2 4 8 16 32 64 128 256 or 512 to get the internal SPI master mode bit rate clock SPI SHIFT REGISTER SHIFT CLOCK SHIFT DIRECTION Rx BUFF...

Page 283: ...ted this pin is not used by the SPI and reverts to being a general purpose port I O pin 14 2 3 MISO Master Data In Slave Data Out When the SPI is enabled as a master and SPI pin control zero SPC0 is 0...

Page 284: ...by their names and a Freescale provided equate or header file is used to translate these names into the appropriate absolute addresses 14 4 1 SPI Control Register 1 SPIxC1 This read write register in...

Page 285: ...erent kinds of synchronous serial peripheral devices Refer to Section 14 5 3 SPI Clock Formats for more details 0 First edge on SPSCK occurs at the middle of the first cycle of an 8 cycle data transfe...

Page 286: ...ts as an input 1 SPI I O pin enabled as an output 1 SPISWAI SPI Stop in Wait Mode 0 SPI clocks continue to operate in wait mode 1 SPI clocks stop when the MCU enters wait mode 0 SPC0 SPI Pin Control 0...

Page 287: ...Table 14 6 SPI Baud Rate Prescaler Divisor SPPR2 SPPR1 SPPR0 Prescaler Divisor 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1 8 Table 14 7 SPI Baud Rate Divisor SPR3 SPR2 SPR1 SPR0 Rat...

Page 288: ...ing a data value to the transmit buffer at SPIxD SPIxS must be read with SPTEF 1 before writing data to SPIxD or the SPIxD write will be ignored SPTEF generates an SPTEF CPU interrupt request if the S...

Page 289: ...1 Master Mode The SPI operates in master mode when the MSTR bit is set Only a master SPI module can initiate transmissions A transmission begins by reading the SPIxS register while SPTEF 1 and writing...

Page 290: ...ack to idle state 14 5 2 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear SPSCK In slave mode SPSCK is the SPI clock input from the master MISO MOSI pin In...

Page 291: ...Register is set NOTE A change of the bits CPOL CPHA SSOE LSBFE MODFEN SPC0 and BIDIROE with SPC0 set in slave mode will corrupt a transmission in progress and has to be avoided 14 5 3 SPI Clock Format...

Page 292: ...1 shows the clock formats when CPHA 0 At the top of the figure the eight bit times are shown for reference with bit 1 starting as the slave is selected SS IN goes low and bit 8 ends at the last SPSCK...

Page 293: ...h shifts in the bit value that was just sampled and shifts the second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave respectively When CPHA 0 the...

Page 294: ...MOSI pin becomes the serial data I O MOMI pin for the master mode and the MISO pin becomes serial data I O SISO pin for the slave mode The MISO pin in master mode and MOSI pin in slave mode are not u...

Page 295: ...e flag bits to determine what event caused the interrupt The service routine should also clear the flag bit s before returning from the ISR usually near the beginning of the ISR 14 5 6 Mode Fault Dete...

Page 296: ...Chapter 12 Serial Peripheral Interface S08SPIV4 MC9S08LG32 MCU Series Rev 5 296 Freescale Semiconductor...

Page 297: ...r or any task scheduling functions It can also serve as a cyclic wake up from low power modes without the need of external components NOTE For details on low power mode operation refer to Table 3 2 in...

Page 298: ...Y DRIVER ANALOG TO DIGITAL CONVERTER ADC 12 BIT AD 15 0 TPM2CH 5 0 TPMCLK TPMCLK LCD24 ADC1 TX2 KBI4 PTA3 LCD23 ADC0 SDA PTA2 LCD22 SCL PTA1 LCD21 PTA0 LG32 16K BYTES LG16 16K BYTES LCD26 ADC3 TPM2CH0...

Page 299: ...terrupt is enabled For lowest possible current consumption the RTC should be stopped by software if not needed as an interrupt source during wait mode 15 1 3 2 Stop Modes The RTC continues to run in s...

Page 300: ...er Refer to the direct page register summary in the memory section of this document for the absolute address assignments for all RTC registers This section refers to registers and control bits only by...

Page 301: ...TC prescaler Changing the clock source clears the prescaler and RTCCNT counters When selecting a clock source ensure that the clock source is properly enabled if applicable to ensure correct operation...

Page 302: ...PO the external clock OSCOUT and the internal clock IRCLK The RTC clock select bits RTCLKS select the desired clock source If a different value is written to RTCLKS the prescaler and RTCCNT counters a...

Page 303: ...for an interrupt to be generated when RTIF is set To enable the real time interrupt set the real time interrupt enable bit RTIE in RTCSC RTIF is cleared by writing a 1 to RTIF 15 4 1 RTC Operation Ex...

Page 304: ...irection to a user on how to initialize and configure the RTC module The example software is implemented in C language The example below shows how to implement time of day with the RTC using the 1 kHz...

Page 305: ...uctor 305 pragma TRAP_PROC void RTC_ISR void Clear the interrupt flag RTCSC byte RTCSC byte 0x80 RTC interrupts every 1 Second Seconds 60 seconds in a minute if Seconds 59 Minutes Seconds 0 60 minutes...

Page 306: ...ighlighted 16 1 1 TPM External Clock The TPM modules on the MC9S08LG32 series use the TPMCLK pin 16 1 2 Module Instances The MC9S08LG32 series MCUs contain two TPM modules TPM1 and TPM2 The memory map...

Page 307: ...27 ADC4 TPM2CH1 KBI7 PTA6 LCD25 ADC2 RX2 KBI5 PTA4 INTERFACE SCI1 TxD1 RxD1 SS SPSCK SCL SDA MOSI MISO VSSA VREFL VDDA VREFH XTAL EXTAL IRQ KBI 7 0 PORT A RESET LIQUID CRYSTAL DISPLAY DRIVER ANALOG TO...

Page 308: ...TPM all channels to switch to center aligned PWM mode When center aligned PWM mode is selected input capture output compare and edge aligned PWM functions are not available on any channels of this TPM...

Page 309: ...signal is called center aligned because the centers of the active duty cycle periods for all channels are aligned with a count value of zero This type of PWM is required for types of motors used in s...

Page 310: ...S MS0B MS0A counter reset CLKSB CLKSA 1 2 4 8 16 32 64 or 128 bus clock external clock synchronizer 16 bit comparator 16 bit latch channel 1 ELS1B ELS1A CH1IE CH1F TPM counter Port logic Interrupt log...

Page 311: ...e mode therefore allowing its use as a timer ELSnB ELSnA 0 0 For proper TPM operation the external clock frequency must not exceed one fourth of the bus clock frequency 16 2 1 2 TPMxCHn TPM Channel n...

Page 312: ...ut signal When ELSnB is set and ELSnA is cleared the TPMxCHn pin is forced high at the start of each new period TPMxCNT 0x0000 and it is forced low when the channel value register matches the TPM coun...

Page 313: ...gister matches the TPM counter and it is cleared when the TPM counter is counting down and the channel value register matches the TPM counter Figure 16 5 High true pulse of a center aligned PWM Figure...

Page 314: ...Timer overflow interrupt enable This read write bit enables TPM overflow interrupts If TOIE is set an interrupt is generated when TOF equals one Reset clears TOIE 0 TOF interrupts inhibited use for s...

Page 315: ...set or any write to the timer status control register TPMxSC Reset clears the TPM counter registers Writing any value to TPMxCNTH or TPMxCNTL also clears the TPM counter TPMxCNTH TPMxCNTL and resets t...

Page 316: ...er modulo registers to 0x0000 that results in a free running timer counter modulo disabled Writes to any of the registers TPMxMODH and TPMxMODL actually writes to buffer registers and the registers ar...

Page 317: ...ence is completed CHnF remains set This is done so a CHnF interrupt request is not lost due to clearing a previous CHnF Reset clears this bit Writing a logic 1 to CHnF has no effect 0 No input capture...

Page 318: ...ge and Level Selection CPWMS MSnB MSnA ELSnB ELSnA Mode Configuration X XX 00 Pin is not controlled by TPM It is reverted to general purpose I O or other peripheral control 0 00 01 Input capture Captu...

Page 319: ...ive or not This latching mechanism allows coherent 16 bit writes in either big endian or little endian order that is friendly to various compiler implementations When BDM is active the coherency mecha...

Page 320: ...ions are properly aligned to bus clock transitions Therefore in order to meet Nyquist criteria considering also jitter the frequency of the external clock source must not exceed 1 4 of the bus clock f...

Page 321: ...ine the basic mode of operation for the corresponding channel Choices include input capture output compare and edge aligned PWM 16 4 2 1 Input Capture Mode With the input capture function the TPM can...

Page 322: ...this PWM signal is determined by ELSnA bit 0 and 100 duty cycle cases are possible The time between the modulus overflow and the channel match value TPMxCnVH TPMxCnVL is the pulse width or duty cycle...

Page 323: ...ificant limitation The resulting period is much longer than required for normal applications All zeros in TPMxMODH TPMxMODL is a special case that must not be used with center aligned PWM mode When CP...

Page 324: ...TPM counter is a free running counter the update is made when the TPM counter changes from 0xFFFE to 0xFFFF When TPMxCNTH TPMxCNTL equals TPMxMODH TPMxMODL the TPM can optionally generate a TOF interr...

Page 325: ...issing the new event 16 6 2 1 Timer Overflow Interrupt TOF Description The meaning and details of operation for TOF interrupts varies slightly depending upon the mode of operation of the TPM system ge...

Page 326: ...is set each time the main timer counter matches the 16 bit value in the channel value register The flag is cleared by the two step sequence described in Section 16 6 2 Description of Interrupt Operati...

Page 327: ...er A timer overflow interrupt can be enabled to generate periodic interrupts for time based software loops Figure 17 1 shows the MC9S08LG32 series block diagram highlighting the MTIM block and pin 17...

Page 328: ...RYSTAL DISPLAY DRIVER ANALOG TO DIGITAL CONVERTER ADC 12 BIT AD 15 0 TPM2CH 5 0 TPMCLK TPMCLK LCD24 ADC1 TX2 KBI4 PTA3 LCD23 ADC0 SDA PTA2 LCD22 SCL PTA1 LCD21 PTA0 LG32 16K BYTES LG16 16K BYTES LCD26...

Page 329: ...efore the MTIM can be used to bring the MCU out of wait mode if the timer overflow interrupt is enabled For lowest possible current consumption the MTIM should be stopped by software if not needed as...

Page 330: ...input must be synchronized by the bus clock Also variations in duty cycle and clock jitter must be accommodated Therefore the TPMCLK signal must be limited to one fourth of the bus frequency The TPMCL...

Page 331: ...n 8 bit clock configuration register An 8 bit counter register An 8 bit modulo register Refer to the direct page register summary in the Chapter 4 Memory for the absolute address assignments for all M...

Page 332: ...OD register 0 MTIM counter has not reached the overflow value in the MTIM modulo register 1 MTIM counter has reached the overflow value in the MTIM modulo register 6 TOIE MTIM Overflow Interrupt Enabl...

Page 333: ...fault to the bus clock BUSCLK 3 0 PS Clock Source Prescaler These four read write bits select one of nine outputs from the 8 bit prescaler Changing the prescaler value while the counter is active does...

Page 334: ...0 0 0 0 0 0 0 0 Figure 17 7 MTIM Modulo Register MTIMMOD Table 17 5 MTIMMOD Field Descriptions Field Description 7 0 MOD MTIM Modulo These eight read write bits contain the modulo value used to reset...

Page 335: ...prescale values are software selectable clock source divided by 1 2 4 8 16 32 64 128 or 256 The prescaler select bits PS 3 0 in MTIMSC select the desired prescale value If the counter is active TSTP 0...

Page 336: ...7 8 the selected clock source could be any of the four possible choices The prescaler is set to PS 0010 or divide by 4 The modulo value in the MTIMMOD register is set to AA When the counter MTIMCNT re...

Page 337: ...nformation so an external development system can reconstruct what happened inside the MCU on a cycle by cycle basis without having external access to the address and data signals 18 1 1 Forcing Active...

Page 338: ...ow the CPU registers to be read or written and allow the user to trace one user instruction at a time or GO to the user program from active background mode Non intrusive commands can be executed at an...

Page 339: ...ed BKGD is a pseudo open drain pin and there is an on chip pullup so no external pullup resistor is required Unlike typical open drain pins the external RC time constant on this pin which is influence...

Page 340: ...ernal BDC clock signal is shown for reference in counting cycles Figure 18 2 shows an external host transmitting a logic 1 or 0 to the BKGD pin of a target HCS08 MCU The host is asynchronous to the ta...

Page 341: ...for the target to recognize it at least two target BDC cycles The host must release the low drive before the target MCU drives a brief active high speedup pulse seven cycles after the perceived start...

Page 342: ...ates the bit time but the target HCS08 finishes it Because the target wants the host to receive a logic 0 it drives the BKGD pin low for 13 BDC clock cycles then briefly drives it high to speed up the...

Page 343: ...ure This nomenclature is used in Table 18 1 to describe the coding structure of the BDC commands Commands begin with an 8 bit hexadecimal command code in the host to target direction most significant...

Page 344: ...rusive E2 RBKP Read BDCBKPT breakpoint register WRITE_BKPT Non intrusive C2 WBKP Write BDCBKPT breakpoint register GO Active BDM 08 d Go to execute the user application program starting at the address...

Page 345: ...munications Typically the host can determine the correct communication speed within a few percent of the actual target speed and the communication protocol can easily tolerate speed errors of several...

Page 346: ...se registers are accessed with dedicated serial BDC commands and are not located in the memory space of the target MCU so they do not have addresses and cannot be accessed by user programs Some of the...

Page 347: ...e commands 6 BDMACT Background Mode Active Status This is a read only status bit 0 BDM not active user application program running 1 BDM active and waiting for serial commands 5 BKPTEN BDC Breakpoint...

Page 348: ...and into active background mode where all BDC commands work Whenever the host forces the target MCU into active background mode the host should issue a READ_STATUS command to check that BDMACT 1 befo...

Page 349: ...ugh serial background mode debug commands not from user programs Reset 0 0 0 0 0 0 0 0 Unimplemented or Reserved Table 18 3 SBDFR Register Field Description Field Description 0 BDFR Background Debug F...

Page 350: ...mode Comparators A and B used to compare addresses Full mode Comparator A compares address and Comparator B compares data Can be used as triggers and or breakpoints Comparator C can be used as a norma...

Page 351: ...Control Registers Tag Force Address Bus 16 0 1 match_A control Read Data Bus Read Write store m u x FIFO Data ppage_sel1 MCU in BDM Change of Flow Indicators subtract 2 m u x Read DBGFH Read DBGFL re...

Page 352: ...igh Register DBGCCH Read write Base 0005 Debug Comparator C Low Register DBGCCL Read write Base 0006 Debug FIFO High Register DBGFH Read only Base 0007 Debug FIFO Low Register DBGFL Read only Base 000...

Page 353: ...Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 DBGFL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DBGCAX RWAEN RWA 0 0 0 0 0 0 DBGCBX RWBEN RWB 0 0 0 0 0 0 DBGCCX RWCEN RWC 0 0 0 0 0 0 reserved 0 0 0 0 0 0 0 0 D...

Page 354: ...BEGIN 0 the bits in this register do not change after reset U U U U U U U U Figure 19 2 Debug Comparator A High Register DBGCAH Table 19 3 DBGCAH Field Descriptions Field Description Bits 15 8 Compar...

Page 355: ...it 8 W POR or non end run 0 0 0 0 0 0 0 0 Reset end run1 1 In the case of an end trace to reset where DBGEN 1 and BEGIN 0 the bits in this register do not change after reset U U U U U U U U Figure 19...

Page 356: ...a if in Full mode 1 Compare corresponding address bit to a logic 1 compares to data if in Full mode Module Base 0x0004 7 6 5 4 3 2 1 0 R Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 W POR or...

Page 357: ...rator C Low compare bits control whether Comparator C will compare the address bus bits 7 0 to a logic 1 or logic 0 0 Compare corresponding address bit to a logic 0 1 Compare corresponding address bit...

Page 358: ...Descriptions Field Description Bits 7 0 FIFO Low Data Bits The FIFO Low data bits contain the least significant byte of data in the FIFO When reading FIFO words read DBGFX and DBGFH before reading DB...

Page 359: ...n 0 0 0 0 0 0 0 0 Reset end run1 1 In the case of an end trace to reset where DBGEN 1 and BEGIN 0 the bits in this register do not change after reset U U U 0 0 0 0 U Unimplemented or Reserved Figure 1...

Page 360: ...U U U 0 0 0 0 U Unimplemented or Reserved Figure 19 12 Debug Comparator C Extension Register DBGCCX Table 19 13 DBGCCX Field Descriptions Field Description 7 RWCEN Read Write Comparator C Enable Bit...

Page 361: ...r not armed 1 Debugger armed 5 TAG Tag or Force Bit The TAG bit controls whether a debugger or comparator C breakpoint will be requested as a tag or force breakpoint to the CPU The TAG bit is not used...

Page 362: ...ion 7 TRGSEL Trigger Selection Bit The TRGSEL bit controls the triggering condition for the comparators See Section 19 4 4 Trigger Break Control TBC for more information 0 Trigger on any compare addre...

Page 363: ...tion 7 AF Trigger A Match Bit The AF bit indicates if Trigger A match condition was met since arming 0 Comparator A did not match 1 Comparator A match 6 BF Trigger B Match Bit The BF bit indicates if...

Page 364: ...stored in the FIFO Table 19 16 shows the correlation between the CNT bits and the amount of valid data in FIFO The CNT will stop after a count to eight even if more data is being stored in the FIFO Th...

Page 365: ...C is used as a third hardware breakpoint and is not involved in the trigger logic for the on chip ICE system In this mode it compares the core address bus with the address stored in the DBGCCH and DBG...

Page 366: ...bit determines whether the breakpoints will be tag type or force type breakpoints To use comparators A and B as hardware breakpoints set DBGT 0x81 for tag type breakpoints and 0x01 for force type brea...

Page 367: ...opcode tracking logic to end the trace run In begin type trace runs BEGIN 1 the start of FIFO capturing is triggered by the qualified comparator signals and the CPU breakpoint if enabled by BRKEN 1 i...

Page 368: ...for A must be met before the match condition for B is compared When the match condition for A or B is met the corresponding flag in the DBGS register is set The A Then Event Only B trigger mode is con...

Page 369: ...g 3 In end trace configurations BEGIN 0 where a CPU breakpoint is enabled BRKEN 1 TRGSEL should agree with TAG In this case where TRGSEL 1 to select opcode tracking qualification and TAG 0 to specify...

Page 370: ...istered during the previous last cycle is decremented by two and stored in the FIFO 19 4 5 3 Storing with End Trigger Storing with End Trigger cannot be used in event only trigger modes Once the DBG m...

Page 371: ...ithout having recorded the change of flow that occurred as part of the interrupt exception Note that the stack will hold the return addresses and can be used to reconstruct execution flow in this scen...

Page 372: ......

Page 373: ...all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in d...

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