NXP Semiconductors MC9S08LG16, Reference Manual

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Chapter 19 Debug Module (DBG) (64K)
MC9S08LG32 MCU Series, Rev. 5
358 Freescale Semiconductor
19.3.2.8 Debug FIFO Low Register (DBGFL)
19.3.2.9 Debug Comparator A Extension Register (DBGCAX)
Module Base + 0x0007
7 6 5 4 3 2 1 0
R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
W
POR
or non-
end-run
0 0 0 0 0 0 0 0
Reset
end-run
1
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
U U U U U U U U
= Unimplemented or Reserved
Figure 19-9. Debug FIFO Low Register (DBGFL)
Table 19-10. DBGFL Field Descriptions
Field Description
Bits 7–0 FIFO Low Data Bits — The FIFO Low data bits contain the least significant byte of data in the FIFO. When
reading FIFO words, read DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the
FIFO pointers to advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX
and DBGFH so it is not necessary to read them before reading DBGFL.
Module Base + 0x0008
7 6 5 4 3 2 1 0
R
RWAEN RWA
0 0 0 0 0 0
W
POR
or non-
end-run
0 0 0 0 0 0 0 0
Reset
end-run
1
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
U U U 0 0 0 0 U
= Unimplemented or Reserved
Figure 19-10. Debug Comparator A Extension Register (DBGCAX)