NXP Semiconductors MC9S08LG16, Reference Manual

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Chapter 16 Internal Clock Source (S08ICSV3)
MC9S08LG32 MCU Series, Rev. 5
240 Freescale Semiconductor
11.4.7 External Reference Clock
The ICS module supports an external reference clock with frequencies between 31.25 kHz to 40 MHz in
all modes. When the ERCLKEN is set, the external reference clock signal will be presented as
ICSERCLK, which can be used as an additional clock source in run mode. When IREFS = 1, the external
reference clock will not be used by the FLL and will only be used as ICSERCLK. In these modes, the
frequency can be equal to the maximum frequency the chip-level timing specifications will support (see
Chapter 1, “Device Overview ”).
If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock source (OSCOUT)
will keep running during stop mode in order to provide a fast recovery upon exiting stop.
11.4.8 Fixed Frequency Clock
The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional clock source.
ICSFFCLK frequency must be no more than 1/4 of the ICSOUT frequency to be valid. Because of this
requirement, in bypass modes the ICSFFCLK is valid only in bypass external modes (FBE and FBELP)
for the following combinations of BDIV, RDIV, and RANGE values:
• RANGE = 1
• BDIV = 00 (divide by 1), RDIV
≥ 010
• BDIV = 01 (divide by 2), RDIV
≥ 011
• BDIV = 10 (divide by 4), RDIV
≥ 100
• BDIV = 11 (divide by 8), RDIV
≥ 101
11.4.9 Local Clock
The ICS presents the low range DCO output clock divided by two as ICSLCLK for use as a clock source
for BDC communications. ICSLCLK is not available in FLL bypassed internal low-power (FBILP) and
FLL bypassed external low-power (FBELP) modes.