NXP Semiconductors MC9S08LG16, Reference Manual

Page: 85 / 373

Chapter 5 Resets, Interrupts, and General System Control
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 85
5.8.5 System Options Register 2 (SOPT2)
This high-page register contains bits to configure MCU specific features on the MC9S08LG32 series
devices.
7 6 5 4 3 2 1 0
R
COPCLKS
1
1
This bit can be written only one time after reset. Additional writes are ignored.
0 0 0 0 0 0
SPIFE
W
Reset: 0 0 0 0 0 0 0 1
= Unimplemented or Reserved
Figure 5-6. System Options Register 2 (SOPT2)
Table 5-7. SOPT2 Register Field Descriptions
Field Description
7
COPCLKS
COP Watchdog Clock Select — This write-once bit selects the clock source of the COP watchdog.
0 Internal 1 kHz clock is source to COP.
1 Bus clock is source to COP.
0
SPIFE
SPI Filter Enable — This bit selects the IFE control of the SPI pins.
0 IFE disabled
1 IFE enabled