NXP Semiconductors MC9S08LG16, Reference Manual

Page: 360 / 373

Chapter 19 Debug Module (DBG) (64K)
MC9S08LG32 MCU Series, Rev. 5
360 Freescale Semiconductor
19.3.2.11 Debug Comparator C Extension Register (DBGCCX)
Module Base + 0x000A
7 6 5 4 3 2 1 0
R
RWCEN RWC
0 0 0 0 0 0
W
POR
or non-
end-run
0 0 0 0 0 0 0 0
Reset
end-run
1
1
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
U U U 0 0 0 0 U
= Unimplemented or Reserved
Figure 19-12. Debug Comparator C Extension Register (DBGCCX)
Table 19-13. DBGCCX Field Descriptions
Field Description
7
RWCEN
Read/Write Comparator C Enable Bit — The RWCEN bit controls whether read or write comparison is enabled
for Comparator C.
0 Read/Write is not used in comparison
1 Read/Write is used in comparison
6
RWC
Read/Write Comparator C Value Bit — The RWC bit controls whether read or write is used in compare for
Comparator C. The RWC bit is not used if RWCEN = 0.
0 Write cycle will be matched
1 Read cycle will be matched