NXP Semiconductors MC9S08LG16, Reference Manual

Page: 194 / 373

Chapter 8 LCD Module (S08LCDLPV1)
MC9S08LG32 MCU Series, Rev. 5
194 Freescale Semiconductor
9.6 Application Information
Figure 9-16 is a programmer’s model of the LCD module. The programmer’s model groups the LCD
module register bit and bit field into functional groups. The model is a high-level illustration of the LCD
module showing the module’s functional hierarchy including initialization and runtime control.
LCDBCTL
XXX-0010 BLINK X Blinking is turned on or off during LCD operation
ALT X Alternate bit is configured during LCD operation
BLANK X Blank bit is configured during LCD operation
BMODE 0 Blink to a blank mode
BRATE[2:0] 010 Select 2 Hz blink frequency using Table 9-17
LCDPEN[5:0] LCDPEN0
LCDPEN1
LCDPEN2
LCDPEN3 11111111
11111111
11111111
00011111 29 LCD pins need to be enabled.
LCDBPEN[5:0] LCDBPEN0
LCDBPEN1
LCDBPEN2
LCDBPEN3 11111111
00000000
00000000
00000000 Eight backplane pins needed.
Note: Any enabled LCD pin can be enabled to operate as a backplane
LCDWF[44:0] LCDWF0
LCDWF1
LCDWF2
LCDWF3
LCDWF4
LCDWF5
LCDWF6
LCDWF7 00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000 Configure which phase the eight backplane pins will be active in. This
configuration sets LCD[0] to be active in Phase A, LCD[1] to be active in
Phase B. . . etc.
This configuration sets LCD pins 0-7 to represent backplane 1-8.
Note: Any backplane pin can be active in any phase
Table 9-25. Initialization Register Values for Example 3 (continued)
Register
bit or
bit field
Binary
Value
Comment