NXP Semiconductors MC9S08LG16, Reference Manual

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Chapter 19 Debug Module (DBG) (64K)
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 365
19.4 Functional Description
This section provides a complete functional description of the on-chip ICE system. The DBG module is
enabled by setting the DBGEN bit in the DBGC register. Enabling the module allows the arming,
triggering and storing of data in the FIFO. The DBG module is made up of three main blocks, the
Comparators, Trigger Break Control logic and the FIFO.
19.4.1 Comparator
The DBG module contains three comparators, A, B, and C. Comparator A compares the core address bus
with the address stored in the DBGCAH and DBGCAL registers. Comparator B compares the core address
bus with the address stored in the DBGCBH and DBGCBL registers except in full mode, where it
compares the data buses to the data stored in the DBGCBL register. Comparator C compares the core
address bus with the address stored in the DBGCCH and DBGCCL registers. Matches on Comparators A,
B, and C are signaled to the Trigger Break Control (TBC) block.
19.4.1.1 RWA and RWAEN in Full Modes
In full modes ("A And B" and "A And Not B") RWAEN and RWA are used to select read or write
comparisons for both comparators A and B. To select write comparisons and the write data bus in Full
Modes set RWAEN=1 and RWA=0, otherwise read comparisons and the read data bus will be selected.
The RWBEN and RWB bits are not used and will be ignored in Full Modes.
19.4.1.2 Comparator C in LOOP1 Capture Mode
Normally comparator C is used as a third hardware breakpoint and is not involved in the trigger logic for
the on-chip ICE system. In this mode, it compares the core address bus with the address stored in the
DBGCCH and DBGCCL registers. However, in LOOP1 capture mode, comparator C is managed by logic
in the DBG module to track the address of the most recent change-of-flow event that was captured into the
FIFO buffer. In LOOP1 capture mode, comparator C is not available for use as a normal hardware
breakpoint.
When the ARM and DBGEN bits are set to one in LOOP1 capture mode, comparator C value registers are
cleared to prevent the previous contents of these registers from interfering with the LOOP1 capture mode
operation. When a COF event is detected, the address of the event is compared to the contents of the
DBGCCH and DBGCCL registers to determine whether it is the same as the previous COF entry in the
capture FIFO. If the values match, the capture is inhibited to prevent the FIFO from filling up with
duplicate entries. If the values do not match, the COF event is captured into the FIFO and the DBGCCH
and DBGCCL registers are updated to reflect the address of the captured COF event.
19.4.2 Breakpoints
A breakpoint request to the CPU at the end of a trace run can be created if the BRKEN bit in the DBGC
register is set. The value of the BEGIN bit in DBGT register determines when the breakpoint request to
the CPU will occur. If the BEGIN bit is set, begin-trigger is selected and the breakpoint request will not
occur until the FIFO is filled with 8 words. If the BEGIN bit is cleared, end-trigger is selected and the
breakpoint request will occur immediately at the trigger cycle.