NXP Semiconductors MC9S08LG16, Reference Manual

Page: 89 / 373

Chapter 5 Resets, Interrupts, and General System Control
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 89
2
PPDACK
Partial Power Down Acknowledge
Writing a logic 1 to PPDACK clears the PPDF bit.
0
PPDC
Partial Power Down Control
This write-once bit controls whether stop2 or stop3 mode is selected.
0 Stop3 mode enabled.
1 Stop2, partial power down mode enabled.
Table 5-12. LVD and LVW Trip Points
Num Characteristic Symbol Min Max Unit
1 High LVD trip point (V
SUPPLY
falling, LVDV = 1)
1
1
All values measured with respect to V
SUPPLY
V
LVDXH
3.90
2
2
All values with factory trim
4.10 V
2 High LVD trip point (V
SUPPLY
rising, LVDV = 1) 4.00 4.20 V
3 Low LVD trip point (V
SUPPLY
falling, LVDV = 0) V
LVDXL
2.48 2.64 V
4 Low LVD trip point (V
SUPPLY
rising, LVDV = 0) 2.54 2.70 V
5 High LVW trip point (V
SUPPLY
falling, {LVDV,LVWV} = 00) V
LVWXLL
2.66 2.82 V
6 High LVW trip point (V
SUPPLY
rising, {LVDV,LVWV} = 00) 2.72 2.88 V
7 Low LVW trip point (V
SUPPLY
falling, {LVDV,LVWV} = 01) V
LVWXLH
2.84 3.00 V
8 Low LVW trip point (V
SUPPLY
rising, {LVDV,LVWV} = 01) 2.90 3.06 V
9 High LVW trip point (V
SUPPLY
falling, {LVDV,LVWV} = 10) V
LVWXHL
4.20 4.40 V
10 High LVW trip point (V
SUPPLY
rising, {LVDV,LVWV} = 10) 4.30 4.50 V
11 Low LVW trip point (V
SUPPLY
falling, {LVDV,LVWV} = 11) V
LVWXHH
4.50 4.70 V
12 Low LVW trip point (V
SUPPLY
rising, {LVDV,LVWV} = 11) 4.60 4.80 V
Table 5-11. SPMSC2 Register Field Descriptions (continued)
Field Description