NXP Semiconductors MC9S08LG16, Reference Manual

Page: 11 / 373

MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 11
Section Number Title Page
5.8.5 System Options Register 2 (SOPT2) ................................................................................85
5.8.6 System Device Identification Register (SDIDH, SDIDL) ................................................86
5.8.7 System Power Management Status and Control 1 Register (SPMSC1) ...........................87
5.8.8 System Power Management Status and Control 2 Register (SPMSC2) ...........................88
5.8.9 System Clock Gating Control 1Register (SCGC1) ...........................................................90
5.8.10 System Clock Gating Control 2 Register (SCGC2) ..........................................................91
5.8.11 Pin Position Control Register (PINPS1) ...........................................................................92
5.8.12 Pin Position Control Register (PINPS2) ...........................................................................93
5.8.13 Pin Position Control Register (PINPS3) ...........................................................................94
5.8.14 Pin Position Control Register (PINPS4) ...........................................................................95
Chapter 6
Parallel Input/Output Control
6.1 Introduction ......................................................................................................................................97
6.2 Pins Shared with LCD......................................................................................................................97
6.3 Port Data and Data Direction ...........................................................................................................97
6.4 Pullup, Slew Rate, and Drive Strength.............................................................................................98
6.4.1 Port Internal Pullup Enable ...............................................................................................98
6.4.2 Port Slew Rate Enable ......................................................................................................99
6.4.3 Port Drive Strength Select ................................................................................................99
6.5 Open Drain Operation ......................................................................................................................99
6.6 Pin Behavior in Stop Modes.............................................................................................................99
6.7 Parallel I/O and Pin Control Registers ...........................................................................................100
6.7.1 Port A Registers ..............................................................................................................100
6.7.2 Port B Registers ..............................................................................................................104
6.7.3 Port C Registers ..............................................................................................................107
6.7.4 Port D Registers ..............................................................................................................110
6.7.5 Port E Registers ..............................................................................................................113
6.7.6 Port F Registers ...............................................................................................................116
6.7.7 Port G Registers ..............................................................................................................119
6.7.8 Port H Registers ..............................................................................................................122
6.7.9 Port I Registers ................................................................................................................125
Chapter 7
Keyboard Interrupt (S08KBIV2)
7.1 Introduction ....................................................................................................................................128
7.1.1 Module Configuration .....................................................................................................128
7.1.2 KBI Clock Gating ...........................................................................................................128
7.1.3 Features ...........................................................................................................................130
7.1.4 Modes of Operation ........................................................................................................130
7.1.5 Block Diagram ................................................................................................................130
7.2 External Signal Description ...........................................................................................................131