NXP Semiconductors MC9S08LG16, Reference Manual

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Chapter 6 Parallel Input/Output Control
MC9S08LG32 MCU Series, Rev. 5
100 Freescale Semiconductor
• In stop3 mode, all I/O is maintained because internal logic circuitry stays powered up. Upon
recovery, normal I/O function is available to the user.
6.7 Parallel I/O and Pin Control Registers
This section provides information about the registers associated with the parallel I/O ports. The data and
data direction registers are located in page zero of the memory map. The pullup, slew rate, and drive
strength control registers are located in the high-page section of the memory map.
Refer to tables in Chapter 4, “Memory ,” for the absolute address assignments for all parallel I/O and their
pin control registers. This section refers to registers and control bits only by their names. A Freescale
Semiconductor-provided equate or header file is normally to translate these names into the appropriate
absolute addresses.
6.7.1 Port A Registers
Port A is controlled by the registers listed below. All the pins of port A are shared with LCD. These pins
have special behavior as explained in
Section 6.2 .