NXP Semiconductors MC9S08LG16, Reference Manual

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Chapter 6 Parallel Input/Output Control
MC9S08LG32 MCU Series, Rev. 5
120 Freescale Semiconductor
6.7.7.3 Port G Pull Enable Register (PTGPE)
6.7.7.4 Port G Slew Rate Enable Register (PTGSE)
7 6 5 4 3 2 1 0
R
PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-34. Internal Pull Enable for Port G Register (PTGPE)
Table 6-33. PTGPE Register Field Descriptions
Field Description
7:0
PTGPE[7:0]
Internal Pull Enable for Port G Bits — Each of these control bits determines if the internal pullup or pulldown
device is enabled for the associated PTG pin. For Port G pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pullup device disabled for Port G bit n.
1 Internal pullup device enabled for Port G bit n.
7 6 5 4 3 2 1 0
R
PTGSE7 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
W
Reset: 1 1 1 1 1 1 1 1
Figure 6-35. Slew Rate Enable for Port G Register (PTGSE)
Table 6-34. PTGSE Register Field Descriptions
Field Description
7:0
PTGSE[7:0]
Output Slew Rate Enable for Port G Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTG pin. For Port G pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for Port G bit n.
1 Output slew rate control enabled for Port G bit n.