NXP Semiconductors MC9S08LG16, Reference Manual

Page: 102 / 373

Chapter 6 Parallel Input/Output Control
MC9S08LG32 MCU Series, Rev. 5
102 Freescale Semiconductor
6.7.1.3 Port A Pull Enable Register (PTAPE)
6.7.1.4 Port A Slew Rate Enable Register (PTASE)
7 6 5 4 3 2 1 0
R
PTAPE7 PTAPE6 PTAPE5 PTAPE4 PTAPE3 PTAPE2 PTAPE1 PTAPE0
W
Reset: 0 0 0 0 0 0 0 0
Figure 6-4. Internal Pull Enable for Port A Register (PTAPE)
Table 6-3. PTAPE Register Field Descriptions
Field Description
7:0
PTAPE[7:0]
Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pullup or pulldown
device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
7 6 5 4 3 2 1 0
R
PTASE7 PTASE6 PTASE5 PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
W
Reset: 1 1 1 1 1 1 1 1
Figure 6-5. Slew Rate Enable for Port A Register (PTASE)
Table 6-4. PTASE Register Field Descriptions
Field Description
7:0
PTASE[7:0]
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.