NXP Semiconductors MC9S08LG16, Reference Manual

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Chapter 5 Resets, Interrupts, and General System Control
MC9S08LG32 MCU Series, Rev. 5
Freescale Semiconductor 79
5.6 Low-Voltage Detect (LVD) System
The MC9S08LG32 series includes a system to protect against low voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system is comprised of a
power-on reset (POR) circuit and a LVD circuit. The LVD circuit is enabled when LVDE in SPMSC1. The
LVD is disabled upon entering either of the stop modes unless LVDSE is set in SPMSC1. If LVDSE and
LVDE are both set, then the MCU enters stop3 instead of stop2, and the current consumption in stop3 with
the LVD enabled is greater.
5.6.1 Power-On Reset Operation
When power is initially applied to the MCU, or when the supply voltage drops below the power-on reset
rearm voltage level, V
POR
, the POR circuit causes a reset condition. As the supply voltage rises, the LVD
circuit holds the MCU in reset until the supply has risen above the low voltage detection low threshold,
V
LVDL
. Both the POR bit and the LVD bit in SRS are set following a POR.
5.6.2 Low-Voltage Detection (LVD) Reset Operation
The LVD can be configured to generate a reset upon detection of a low voltage condition by setting
LVDRE to 1. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply
voltage has risen above the low voltage detection threshold. The LVD bit in the SRS register is set
following either an LVD reset or POR.
5.6.3 Low-Voltage Warning (LVW) Interrupt Operation
The LVD system has a low voltage warning flag (LVWF) to indicate to you that the supply voltage is
approaching, but remains above, the LVD voltage. The LVW has an interrupt associated with it, enabled
by setting the LVWIE bit in the SPMSC1 register. If enabled, an LVW interrupt request occurs when the
LVWF is set. LVWF is cleared by writing a 1 to the LVWACK bit in SPMSC1 provided the LVW condition
no longer exists.
5.7 Peripheral Clock Gating
The MC9S08LG32 series includes a clock gating system to manage the bus clock sources to the individual
peripherals. Using this system, you can enable or disable the bus clock to each of the peripherals at the
clock source, eliminating unnecessary clocks to peripherals which are not in use and thereby reducing the
overall run and wait mode currents.
Out of reset, all peripheral clocks are disabled. For lowest possible run or wait currents, user software must
disable the clock source to any peripheral not in use. The actual clock is enabled or disabled immediately
following the write to the Clock Gating Control registers (SCGC1 and SCGC2). Any peripheral with a
gated clock cannot be used unless its clock is enabled. Writing to the registers of a peripheral with a
disabled clock has no effect.