DR
AFT
DR
AFT
DRAFT
DR
D
RAFT
DRAFT
DRA
FT DRAF
D
RAFT DRAFT DRAFT DRAFT DRAFT D
DRAFT
D
RAFT DRA
FT DRAFT DRAFT DRAFT DRA
UM10316_0
© NXP B.V. 2008. All rights reserved.
User manual
Rev. 00.06 — 17 December 2008
62 of 571
NXP Semiconductors
UM10316
Chapter 5: LPC29xx Power Management Unit (PMU)
BASE_SYS_CLK
CLK_SYS_CPU
+
+
1
CLK_SYS
+
+
1
CLK_SYS_PCR
+
+
1
CLK_SYS_FMC
+
+
+
CLK_SYS_RAM0
+
+
+
CLK_SYS_RAM1
+
+
+
CLK_SYS_SMC
+
+
+
CLK_SYS_GESS
+
+
+
CLK_SYS_VIC
+
+
+
CLK_SYS_PESS
+
+
+
CLK_SYS_GPIO0
+
+
+
CLK_SYS_GPIO1
+
+
+
CLK_SYS_GPIO2
+
+
+
CLK_SYS_GPIO3
+
+
+
CLK_SYS_IVNSS_A
+
+
+
CLK_SYS_MSCSS_A
+
+
+
CLK_SYS_GPIO4
+
+
+
CLK_SYS_GPIO5
+
+
+
CLK_SYS_DMA
+
+
+
CLK_SYS_USB
+
+
+
BASE_PCR_CLK
CLK_PCR_SLOW
+
+
1
BASE_IVNSS_CLK
CLK_IVNSS_APB
+
+
+
CLK_IVNSS_CANCA
+
+
+
CLK_IVNSS_CANC0
+
+
+
CLK_IVNSS_CANC1
+
+
+
CLK_IVNSS_I2C0
+
+
+
CLK_IVNSS_I2C1
+
+
+
CLK_IVNSS_LIN0
+
+
+
CLK_IVNSS_LIN1
+
+
+
BASE_MSCSS_CLK
CLK_MSCSS_APB
+
+
+
CLK_MSCSS_MTMR0
+
+
+
CLK_MSCSS_MTMR1
+
+
+
CLK_MSCSS_PWM0
+
+
+
CLK_MSCSS_PWM1
+
+
+
CLK_MSCSS_PWM2
+
+
+
CLK_MSCSS_PWM3
+
+
+
Table 49.
Branch clock overview
…continued
Legend:
‘1’ Indicates that the related register bit is tied off to logic HIGH, all writes are ignored
‘0’ Indicates that the related register bit is tied off to logic LOW, all writes are ignored
‘+’ Indicates that the related register bit is readable and writable
Base clock
Branch clock name/clock leafs
Implemented switch on/off
mechanism
WAKE-UP
AUTO
RUN
