NXP Semiconductors KE1xF Series, Reference Manual, Page: 450 / 1483

• SPLLDIV1_CLK / SPLLDIV2_CLK
• FIRCDIV1_CLK / SCG_FIRCDIV2_CLK
• SIRCDIV1_CLK / SIRCDIV2_CLK
• SOSCDIV1_CLK / SOSCDIV2_CLK
See the Clock Distribution Chapter for more information.
19.3 Memory Map/Register Definition
This section includes the memory map and register definition.
The SCG registers can only be written when in supervisor mode. Write accesses when in
user mode will result in a bus transfer error. Read accesses may be performed in both
supervisor and user mode.
NOTE
For any writeable SCG registers, only 32-bit writes are allowed.
8-bit or 16-bit writes will result in transfer errors.
SCG memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4006_4000 Version ID Register (SCG_VERID) 32 R 0100_0000h 19.3.1/451
4006_4004 Parameter Register (SCG_PARAM) 32 R See section 19.3.2/451
4006_4010 Clock Status Register (SCG_CSR) 32 R See section 19.3.3/452
4006_4014 Run Clock Control Register (SCG_RCCR) 32 R/W See section 19.3.4/454
4006_4018 VLPR Clock Control Register (SCG_VCCR) 32 R/W See section 19.3.5/457
4006_401C HSRUN Clock Control Register (SCG_HCCR) 32 R/W See section 19.3.6/459
4006_4020
SCG CLKOUT Configuration Register
(SCG_CLKOUTCNFG)
32 R/W 0300_0000h 19.3.7/461
4006_4100 System OSC Control Status Register (SCG_SOSCCSR) 32 R/W See section 19.3.8/462
4006_4104 System OSC Divide Register (SCG_SOSCDIV) 32 R/W 0000_0000h 19.3.9/464
4006_4108 System Oscillator Configuration Register (SCG_SOSCCFG) 32 R/W 0000_0010h 19.3.10/465
4006_4200 Slow IRC Control Status Register (SCG_SIRCCSR) 32 R/W 0100_0005h 19.3.11/467
4006_4204 Slow IRC Divide Register (SCG_SIRCDIV) 32 R/W 0000_0000h 19.3.12/468
4006_4208 Slow IRC Configuration Register (SCG_SIRCCFG) 32 R/W 0000_0001h 19.3.13/469
4006_4300 Fast IRC Control Status Register (SCG_FIRCCSR) 32 R/W See section 19.3.14/470
4006_4304 Fast IRC Divide Register (SCG_FIRCDIV) 32 R/W 0000_0000h 19.3.15/472
4006_4308 Fast IRC Configuration Register (SCG_FIRCCFG) 32 R/W 0000_0000h 19.3.16/473
4006_430C Fast IRC Trim Configuration Register (SCG_FIRCTCFG) 32 R/W 0000_0000h 19.3.17/474
4006_4318 Fast IRC Status Register (SCG_FIRCSTAT) 32 R/W See section 19.3.18/475
Table continues on the next page...
Memory Map/Register Definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
450 NXP Semiconductors