NXP Semiconductors KE1xF Series, Reference Manual, Page: 325 / 1483

14.3 Memory Map/Register Definition
The cache programmer's model provides a variety of registers for configuring and
controlling the cache, as well as indirect access paths to all cache tag and data storage.
LMEM memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
E008_2000 Cache control register (LMEM_PCCCR) 32 R/W 0000_0000h 14.3.1/325
E008_2004 Cache line control register (LMEM_PCCLCR) 32 R/W 0000_0000h 14.3.2/326
E008_2008 Cache search address register (LMEM_PCCSAR) 32 R/W 0000_0000h 14.3.3/329
E008_200C Cache read/write value register (LMEM_PCCCVR) 32 R/W 0000_0000h 14.3.4/330
E008_2020 Cache regions mode register (LMEM_PCCRMR) 32 R/W AA0F_A000h 14.3.5/330
14.3.1 Cache control register (LMEM_PCCCR)
Address: E008_2000h base + 0h offset = E008_2000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
GO
0
PUSHW1
INVW1
PUSHW0
INVW0
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PCCR3 PCCR2
ENWRBUF
ENCACHE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LMEM_PCCCR field descriptions
Field Description
31
GO
Initiate Cache Command
Setting this bit initiates the cache command indicated by bits 27-24. Reading this bit indicates if a
command is active
NOTE: This bit stays set until the command completes. Writing zero has no effect.
0 Write: no effect. Read: no cache command active.
1 Write: initiate command indicated by bits 27-24. Read: cache command active.
Table continues on the next page...
Chapter 14 Local Memory Controller (LMEM)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 325