NXP Semiconductors KE1xF Series, Reference Manual, Page: 994 / 1483

FTMx_COMBINE field descriptions (continued)
Field Description
DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and
when the capture of channel (n+1) event is made.
0 The dual edge captures are inactive.
1 The dual edge captures are active.
18
DECAPEN2
Dual Edge Capture Mode Enable For n = 4
Enables the Dual Edge Capture mode in the channels (n) and (n+1). See Channel Modes .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
17
COMP2
Complement Of Channel (n) For n = 4
In Complementary mode the channel (n+1) output is the inverse of the channel (n) output.
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The channel (n+1) output is the same as the channel (n) output.
1 The channel (n+1) output is the complement of the channel (n) output.
16
COMBINE2
Combine Channels For n = 4
Used on the selection of the combine mode for channels (n) and (n+1). See Channel Modes .
This field is write protected. It can be written only when MODE[WPDIS] = 1.
15
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
14
FAULTEN1
Fault Control Enable For n = 2
Enables the fault control in channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The fault control in this pair of channels is disabled.
1 The fault control in this pair of channels is enabled.
13
SYNCEN1
Synchronization Enable For n = 2
Enables PWM synchronization of registers C(n)V and C(n+1)V.
0 The PWM synchronization in this pair of channels is disabled.
1 The PWM synchronization in this pair of channels is enabled.
12
DTEN1
Deadtime Enable For n = 2
Enables the deadtime insertion in the channels (n) and (n+1).
This field is write protected. It can be written only when MODE[WPDIS] = 1.
0 The deadtime insertion in this pair of channels is disabled.
1 The deadtime insertion in this pair of channels is enabled.
11
DECAP1
Dual Edge Capture Mode Captures For n = 2
Enables the capture of the FTM counter value according to the channel (n) input event and the
configuration of the dual edge capture bits.
This field applies only when DECAPEN = 1.
DECAP bit is cleared automatically by hardware if Dual Edge Capture – One-Shot mode is selected and
when the capture of channel (n+1) event is made.
Table continues on the next page...
Memory map and register definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
994 NXP Semiconductors