NXP Semiconductors KE1xF Series, Reference Manual, Page: 1062 / 1483

The SWOCTRL register can be updated at each rising edge of FTM input clock (SWOC
= 0) or by the enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1)
according to the following flowchart.
In the case of enhanced PWM synchronization, the SWOCTRL register synchronization
depends on SWSOC and HWSOC bits.
end
begin
= 1
= 0
end end
end
end
end
= 1
= 0
= 1
= 1
= 0
= 0
= 1
SWOCTRL is updated
by software trigger
software
trigger
hardware
trigger
SWOCTRL is updated
by hardware trigger
enhanced PWM synchronization
update SWOCTRL register by
PWM synchronization
update SWOCTRL register at
each rising edge of FTM input clock
= yes
0 =
1 =
0 =
0 =
no =
1 =
SWOC
bit ?
SYNCMODE
bit ?
rising edge
of FTM input
clock ?
update SWOCTRL
with its buffer value
update SWOCTRL
with its buffer value
HWSOC
bit ?
TRIGn
bit ?
wait hardware trigger n
update SWOCTRL
with its buffer value
HWTRIGMODE
bit ?
clear TRIGn bit
SWSOC
bit ?
SWSYNC
bit ?
Figure 41-57. SWOCTRL register synchronization flowchart
Functional description
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
1062 NXP Semiconductors