NXP Semiconductors KE1xF Series, Reference Manual, Page: 96 / 1483

MCM_FATR field descriptions (continued)
Field Description
7
BEWT
Bus error write
Indicates the type of system bus access when the error was detected. Since this logic is monitoring data
transfers from the cache write buffer, this bit is always a logical one, signaling a write operation.
0 Read access
1 Write access
6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5–4
BESZ
Bus error size
Indicates the size of the cache write buffer access when the error was detected.
00 8-bit access
01 16-bit access
10 32-bit access
11 Reserved
3–2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
BEMD
Bus error privilege level
Indicates the privilege level of the cache write buffer access when the error was detected.
0 User mode
1 Supervisor/privileged mode
0
BEDA
Bus Error Data Access type
Indicates the type of cache write buffer access when the error was detected. This attribute is always a
logical one signaling a data reference.
0 Instruction
1 Data
6.2.7 Store Buffer Fault Data Register (MCM_FDR)
When a properly-enabled cache write buffer error interrupt event is detected, the faulting
data is captured in the MCM_FDR register.
The bits in this register are set by hardware and signaled by the assertion of
MCM_ISCR[CWBER]. For byte and halfword writes, only the accessed byte lanes
contain valid data; the contents of the other bytes are undefined. Attempted writes have
no effect.
Memory map/register descriptions
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
96 NXP Semiconductors