NXP Semiconductors KE1xF Series, Reference Manual, Page: 99 / 1483

MCM_CPO field descriptions (continued)
Field Description
0 Request is cleared.
1 Request Compute Operation.
6.2.10 Local Memory Descriptor Register (MCM_LMDRn)
NOTE
The LMDRn registers mapping to the LMEMs is as follows:
• LMDR0: SRAM_L
• LMDR1: SRAM_U
• LMDR2: PC CACHE
This section of the programming model is an array of 32-bit generic on-chip memory
descriptor registers that provide static information on the attached memories as well as
configurable controls (where appropriate).
Privileged 32-bit reads from a processor core or the debugger return the appropriate
processor information. Reads from any other bus master return all zeroes. Privileged
writes from a processor core or the debugger to writeable registers update the appropriate
fields. Privileged writes from other bus masters are ignored. Attempted user mode
accesses or any access with a size other than 32 bits are terminated with an error.
Chapter 6 Miscellaneous Control Module (MCM)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 99