NXP Semiconductors KE1xF Series, Reference Manual, Page: 1411 / 1483

CANx_ESR1 field descriptions (continued)
Field Description
6
TX
FlexCAN In Transmission
This bit indicates if FlexCAN is transmitting a message. See the table in the overall CAN_ESR1 register
description.
0 FlexCAN is not transmitting a message.
1 FlexCAN is transmitting a message.
5–4
FLTCONF
Fault Confinement State
This 2-bit field indicates the Confinement State of the FlexCAN module.
If the LOM bit in the Control Register 1 is asserted, after some delay that depends on the CAN bit timing
the FLTCONF field will indicate “Error Passive”. Because of the very same delay, the way in which
FLTCONF reflects an update to the CAN_ECR register by the CPU, also gets affected.
This bit field is affected by soft reset, but if the LOM bit is asserted, its reset value lasts just one CAN bit.
After this time, FLTCONF reports "Error Passive".
00 Error Active
01 Error Passive
1x Bus Off
3
RX
FlexCAN In Reception
This bit indicates if FlexCAN is receiving a message. See the table in the overall CAN_ESR1 register
description.
0 FlexCAN is not receiving a message.
1 FlexCAN is receiving a message.
2
BOFFINT
Bus Off Interrupt
This bit is set when FlexCAN enters ‘Bus Off’ state. If the corresponding mask bit in the Control Register 1
(CAN_CTRL1[BOFFMSK]) is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1.
Writing 0 has no effect.
0 No such occurrence.
1 FlexCAN module entered Bus Off state.
1
ERRINT
Error Interrupt
This bit indicates that at least one of the Error Bits (BIT1ERR, BIT0ERR, ACKERR. CRCERR, FRMERR
or STFERR) is set. If the corresponding mask bit CAN_CTRL1[ERRMSK] is set, an interrupt is generated
to the CPU. This bit is cleared by writing it to 1. Writing 0 has no effect.
0 No such occurrence.
1 Indicates setting of any Error Bit in the Error and Status Register.
0
WAKINT
Wake-Up Interrupt
This field applies when FlexCAN is in low-power mode under Self Wake Up mechanism:
• Stop mode
When a recessive-to-dominant transition is detected on the CAN bus and if the CAN_MCR[WAKMSK] bit
is set, an interrupt is generated to the CPU. This bit is cleared by writing it to 1.
When CAN_MCR[SLFWAK] is negated, this flag is masked. The CPU must clear this flag before disabling
the bit. Otherwise it will be set when the SLFWAK is set again. Writing 0 has no effect.
Table continues on the next page...
Chapter 50 CAN (FlexCAN)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 1411