NXP Semiconductors KE1xF Series, Reference Manual, Page: 1370 / 1483

The receive shift register will assert an error interrupt if a NACK is detected, but software
is responsible for generating the STOP or repeated START condition. If a NACK is
detected during master-transmit, the interrupt routine should immediately write the
transmit shifter register with 0x00 (if generating STOP) or 0xFF (if generating repeated
START). Software should then wait for the next rising edge on SCL and then disable
both timers. The transmit shifter should then be disabled after waiting the setup delay for
a repeated START or STOP condition.
Due to synchronization delays, the data valid time for the transmit output is 2 FlexIO
clock cycles, so the maximum baud rate is divide by 6 of the FlexIO clock frequency.
The I2C master data valid is delayed 2 cycles because the clock output is passed through
a synchronizer before clocking the transmit/receive shifter (to guarantee some SDA hold
time). Since the SCL output is synchronous with FlexIO clock, the synchronization delay
is 1 cycle and then 1 cycle to generate the output.
Table 49-10. I2C Master Configuration
Register Value Comments
SHIFTCFGn 0x0000_0032 Start bit enabled (logic 0) and stop bit
enabled (logic 1).
SHIFTCTLn 0x0101_0082 Configure transmit using Timer 1 on
rising edge of clock with inverted output
enable (open drain output) on Pin 0.
SHIFTCFG(n+1) 0x0000_0020 Start bit disabled and stop bit enabled
(logic 0) for ACK/NACK detection.
SHIFTCTL(n+1) 0x0180_0001 Configure receive using Timer 1 on
falling edge of clock with input data on
Pin 0.
TIMCMPn 0x0000_2501 Configure 2 word transfer with baud rate
of divide by 4 of the FlexIO clock. Set
TIMCMP[15:8] = (number of words x 18)
+ 1. Set TIMCMP[7:0] = (baud rate
divider / 2) - 1.
TIMCFGn 0x0102_2222 Configure start bit, stop bit, enable on
trigger high, disable on compare, reset if
output equals pin. Initial clock state is
logic 0 and is not affected by reset.
TIMCTLn 0x01C1_0101 Configure dual 8-bit counter using Pin 1
output enable (SCL open drain), with
Shifter 0 flag as the inverted trigger.
TIMCMP(n+1) 0x0000_000F Configure 8-bit transfer. Set
TIMCMP[15:0] = (number of bits x 2) - 1.
TIMCFG(n+1) 0x0020_1112 Enable when Timer 0 is enabled, disable
when Timer 0 is disabled, enable start
bit and stop bit at end of each word,
decrement on pin input.
TIMCTL(n+1) 0x01C0_0183 Configure 16-bit counter using inverted
Pin 1 input (SCL).
Table continues on the next page...
Application Information
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
1370 NXP Semiconductors