NXP Semiconductors KE1xF Series, Reference Manual, Page: 441 / 1483

Table 18-1. Peripheral Clock Summary (continued)
Module Name Bus Interface
Clock Gating
Peripheral Functional Clock
1
Max Frequency of Clock Source
Gated by
[CGC] bit of
PCC
Clocks controlled
by [PCS] bits of
PCC
Clocks controlled by
registers inside
module
CRC Yes BUS_CLK Max: BUS_CLK
GPIOC Yes SYS_CLK Max: SYS_CLK
DMA Yes SYS_CLK Max: SYS_CLK
Memory Modules
FTFE Yes FLASH_CLK Max: FLASH_CLK
SYS RAM No SYS_CLK Max: SYS_CLK
Analog Modules
ADC0–ADC2 Yes SIRC_CLK,FIRC_C
LK,SPLL_CLK,
SOSC_CLK - Max: 50 MHz
DAC0 Yes BUS_CLK Max: BUS_CLK
ACMP0–ACMP2 Yes BUS_CLK Max: BUS_CLK
1. The clock sources undergo clock divider DIV x in SCG. For details, see the "High-Level clocking diagram" section in the
Clocking chapter and the "Chip-specific information" section in the respective module chapter.
18.6.1 LPO clock distribution
PMC
LPO128K
÷128
1 kHz
128 kHz
WDOG
EWM
LPTMR
RTC
PORT Control
18.6.2 EWM clocks
This table shows the EWM clocks and the corresponding chip clocks.
Table 18-2. EWM clock connections
Module clock Chip clock
Low Power Clock 128 kHz LPO Clock (LPO_CLK)
Chapter 18 Clock Distribution
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 441