NXP Semiconductors KE1xF Series, Reference Manual, Page: 264 / 1483

DMA_HRS field descriptions (continued)
Field Description
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 2 is not present
1 A hardware service request for channel 2 is present
1
HRS1
Hardware Request Status Channel 1
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 1 is not present
1 A hardware service request for channel 1 is present
0
HRS0
Hardware Request Status Channel 0
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 0 is not present
1 A hardware service request for channel 0 is present
12.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS)
Address: 4000_8000h base + 44h offset = 4000_8044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
EDREQ_15 EDREQ_14 EDREQ_13 EDREQ_12 EDREQ_11 EDREQ_10
EDREQ_9 EDREQ_8 EDREQ_7 EDREQ_6 EDREQ_5 EDREQ_4 EDREQ_3 EDREQ_2 EDREQ_1 EDREQ_0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_EARS field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory map/register definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
264 NXP Semiconductors