NXP Semiconductors KE1xF Series, Reference Manual, Page: 781 / 1483

35.4 External signal description
The table found here describes the PORT external signal.
Table 35-2. Signal properties
Name Function I/O Reset Pull
PORTx[31:0] External interrupt I/O 0 -
NOTE
Not all pins within each port are implemented on each device.
35.5 Detailed signal description
The table found here contains the detailed signal description for the PORT interface.
Table 35-3. PORT interface—detailed signal description
Signal I/O Description
PORTx[31:0] I/O External interrupt.
State meaning
Asserted—pin is logic 1.
Negated—pin is logic 0.
Timing Assertion—may occur at any time and can assert
asynchronously to the system clock.
Negation—may occur at any time and can assert
asynchronously to the system clock.
35.6 Memory map and register definition
Any read or write access to the PORT memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states.
PORT memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_9000 Pin Control Register n (PORTA_PCR0) 32 R/W See section 35.6.1/788
4004_9004 Pin Control Register n (PORTA_PCR1) 32 R/W See section 35.6.1/788
4004_9008 Pin Control Register n (PORTA_PCR2) 32 R/W See section 35.6.1/788
Table continues on the next page...
Chapter 35 Port Control and Interrupts (PORT)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 781