NXP Semiconductors KE1xF Series, Reference Manual, Page: 207 / 1483

10.4.2.3.3 Fields
Field Function
31
LK
Enable
This bit shows whether the register can be written or not.
0b - Register can be written.
1b - Register cannot be written until the next system Reset.
30-24
SEL3
Trigger MUX Input 3 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 3. Refer to the
Select Bit Fields table in the Features section for bit field information.
23
—
This read-only bit field is reserved and always has the value 0.
22-16
SEL2
Trigger MUX Input 2 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 2. Refer to the
Select Bit Fields table in the Features section for bit field information.
15
—
This read-only bit field is reserved and always has the value 0.
14-8
SEL1
Trigger MUX Input 1 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 1. Refer to the
Select Bit Fields table in the Features section for bit field information.
7
—
This read-only bit field is reserved and always has the value 0.
6-0
SEL0
Trigger MUX Input 0 Source Select
This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the
Select Bit Fields table in the Features section for bit field information.
10.5 Usage Guide
The TRGMUX is an extremely flexible module interconnectivity scheme. The trigger
source could be from various peripherals and external input pins, to multiple pins/
peripherals. The module level interconnections and trigger scheme offload the
intervention of CPU, which is also useful when CPU is in WAIT/STOP mode. The
following are some typical use-cases for TRGMUX.
10.5.1 ADC Trigger Source
The following triggers are via the TRGMUX:
• CMP out to trigger each ADC
• LPIT capable to trigger each ADC
Chapter 10 Trigger MUX Control (TRGMUX)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 207