NXP Semiconductors KE1xF Series, Reference Manual, Page: 249 / 1483

12.3.9 Clear Enable Error Interrupt Register (DMA_CEEI)
The CEEI provides a simple memory-mapped mechanism to clear a given bit in the EEI
to disable the error interrupt for a given channel. The data value on a register write causes
the corresponding bit in the EEI to be cleared. Setting the CAEE bit provides a global
clear function, forcing the EEI contents to be cleared, disabling all DMA request inputs.
If the NOP bit is set, the command is ignored. This allows you to write multiple-byte
registers as a 32-bit word. Reads of this register return all zeroes.
Address: 4000_8000h base + 18h offset = 4000_8018h
Bit 7 6 5 4 3 2 1 0
Read 0 0 0
Write NOP CAEE 0 CEEI
Reset 0 0 0 0 0 0 0 0
DMA_CEEI field descriptions
Field Description
7
NOP
No Op enable
0 Normal operation
1 No operation, ignore the other bits in this register
6
CAEE
Clear All Enable Error Interrupts
0 Clear only the EEI bit specified in the CEEI field
1 Clear all bits in EEI
5–4
Reserved
This field is reserved.
CEEI Clear Enable Error Interrupt
Clears the corresponding bit in EEI
Chapter 12 Enhanced Direct Memory Access (eDMA)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 249