NXP Semiconductors KE1xF Series, Reference Manual, Page: 459 / 1483

SCG_VCCR field descriptions (continued)
Field Description
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
19.3.6 HSRUN Clock Control Register (SCG_HCCR)
This register controls the system clock source and the system clock dividers for the core,
platform, external and bus clock domains when in HSRUN mode only. This register can
only be written using a 32-bit write. Selecting a different clock source when in HSRUN
requires that clock source to be enabled first and be valid before system clocks switch to
that clock source. If system clock divide ratios also change when selecting a different
clock mode when in HSRUN, new system clock divide ratios will not take affect until
new clock source is valid.
Address: 4006_4000h base + 1Ch offset = 4006_401Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
SCS
0
DIVCORE Reserved
0
DIVBUS DIVSLOW
W
Reset
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
SCG_HCCR field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27–24
SCS
System Clock Source
Selects the clock source generating the system clock in HSRUN mode. Attempting to select a clock that is
not valid will be ignored. Selecting a different clock source when in HSRUN mode will enable that clock
source and switch to that clock mode when it is valid.
0000 Reserved
0001 System OSC (SOSC_CLK)
0010 Slow IRC (SIRC_CLK)
0011 Fast IRC (FIRC_CLK)
0100 Reserved
0101 Reserved
0110 System PLL (SPLL_CLK)
0111 Reserved
Table continues on the next page...
Chapter 19 System Clock Generator (SCG)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 459