NXP Semiconductors KE1xF Series, Reference Manual, Page: 140 / 1483

9.2.1 Features
Key features of the peripheral bridge are:
• Supports peripheral slots with 8-, 16-, and 32-bit datapath width
• Programming model provides memory protection functionality
9.2.2 General operation
The slave devices connected to the peripheral bridge are modules which contain a
programming model of control and status registers. The system masters read and write
these registers through the peripheral bridge.
The register maps of the peripherals are located on 4-KB boundaries. Each peripheral is
allocated one or more 4-KB block(s) of the memory map. Two global external module
enables are available for the remaining address space to allow for customization and
expansion of addressed peripheral devices.
9.3 Memory map/register definition
The 32-bit peripheral bridge registers can be accessed only in supervisor mode by trusted
bus masters. Additionally, these registers must be read from or written to only by a 32-bit
aligned access. The peripheral bridge registers are mapped into the Peripheral Access
Control Register A PACRA[PACR0] address space.
AIPS memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_0000 Master Privilege Register A (AIPS_MPRA) 32 R/W See section 9.3.1/141
4000_0020 Peripheral Access Control Register (AIPS_PACRA) 32 R/W See section 9.3.2/144
4000_0024 Peripheral Access Control Register (AIPS_PACRB) 32 R/W See section 9.3.2/144
4000_0028 Peripheral Access Control Register (AIPS_PACRC) 32 R/W See section 9.3.2/144
4000_002C Peripheral Access Control Register (AIPS_PACRD) 32 R/W See section 9.3.2/144
4000_0040
Off-Platform Peripheral Access Control Register
(AIPS_OPACRA)
32 R/W See section 9.3.3/149
4000_0044
Off-Platform Peripheral Access Control Register
(AIPS_OPACRB)
32 R/W See section 9.3.3/149
4000_0048
Off-Platform Peripheral Access Control Register
(AIPS_OPACRC)
32 R/W See section 9.3.3/149
Table continues on the next page...
Memory map/register definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
140 NXP Semiconductors