NXP Semiconductors KE1xF Series, Reference Manual, Page: 1402 / 1483

50.4.5 Rx Mailboxes Global Mask Register (CANx_RXMGMASK)
This register is located in RAM.
RXMGMASK is provided for legacy application support.
• When the CAN_MCR[IRMQ] bit is negated, RXMGMASK is always in effect (the
bits in the MG field will mask the Mailbox filter bits).
• When the CAN_MCR[IRMQ] bit is asserted, RXMGMASK has no effect (the bits in
the MG field will not mask the Mailbox filter bits).
RXMGMASK is used to mask the filter fields of all Rx MBs, excluding MBs 14-15,
which have individual mask registers.
This register can only be written in Freeze mode as it is blocked by hardware in other
modes.
Address: Base a 10h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MG
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset. •
CANx_RXMGMASK field descriptions
Field Description
MG Rx Mailboxes Global Mask Bits
These bits mask the Mailbox filter bits. Note that the alignment with the ID word of the Mailbox is not
perfect as the two most significant MG bits affect the fields RTR and IDE, which are located in the Control
and Status word of the Mailbox. The following table shows in detail which MG bits mask each Mailbox filter
field.
SMB[RTR]
1
CAN_CTRL2[
RRS]
CAN_CTRL2[
EACEN]
Mailbox filter fields
MB[RTR] MB[IDE] MB[ID] Reserved
0 - 0 note
2
note
3
MG[28:0] MG[31:29]
0 - 1 MG[31] MG[30] MG[28:0] MG[29]
1 0 - - - - MG[31:0]
1 1 0 - - MG[28:0] MG[31:29]
1 1 1 MG[31] MG[30] MG[28:0] MG[29]
0 The corresponding bit in the filter is "don't care."
1 The corresponding bit in the filter is checked.
Memory map/register definition
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
1402 NXP Semiconductors