NXP Semiconductors KE1xF Series, Reference Manual, Page: 479 / 1483

SCG_SPLLDIV field descriptions (continued)
Field Description
101 Divide by 16
110 Divide by 32
111 Divide by 64
19.3.21 System PLL Configuration Register (SCG_SPLLCFG)
The SPLLCFG register cannot be changed when the System PLL is enabled. When the
System PLL is enabled, writes to this register are ignored, and there is no transfer error.
The below information applies to VCO_CLK.
The SPLL_CLK = (VCO_CLK)/2
The VCO_CLK = SPLL_SOURCE/( 1) X (MULT + 16)
SPLL_SOURCE is the clock source selected from the SOURCE bitfield of this register.
Address: 4006_4000h base + 608h offset = 4006_4608h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
MULT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PREDIV
0
SOURCE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCG_SPLLCFG field descriptions
Field Description
31–21
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
20–16
MULT System PLL Multiplier
Table continues on the next page...
Chapter 19 System Clock Generator (SCG)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 479