NXP Semiconductors KE1xF Series, Reference Manual, Page: 554 / 1483

22.2.2.2 Low voltage detect (LVD)
The chip includes a system for managing low voltage conditions to protect memory
contents and control MCU system states during supply voltage variations. The system
consists of a power-on reset (POR) circuit and an LVD circuit. The LVD system can
always be enabled in HSRUN, normal Run, or Wait mode. The LVD system is disabled
(LVR active only) when entering VLPx modes or Stop mode.
The LVD can be configured to generate a reset upon detection of a low voltage condition
by setting the PMC_LVDSC1[LVDRE] bit to 1. After an LVD reset has occurred, the
LVD system holds the MCU in reset until the supply voltage has risen above the low
voltage detection threshold. The RCM_SRS[LVD] bit is set following either an LVD
reset or POR.
Refer to the "Low-voltage Detect (LVD) System" section in the Power Management
Controller (PMC) chapter for more information. For LVR related content, see
Low
Voltage Reset (LVR) Operation .
22.2.2.3 Watchdog timer (WDOG)
The watchdog timer (WDOG) monitors the operation of the system by expecting periodic
communication from the software. This communication is generally known as servicing
(or refreshing) the watchdog. If this periodic refreshing does not occur, the watchdog
issues a system reset. The reset causes the RCM_SRS[WDOG] bit to set.
22.2.2.4 Clock generator loss-of-clock (LOC)
The SCG module contains a clock monitor with reset and interrupt request capability for
ROSC (OSC32) and SOSC clocks.
NOTE
To prevent unexpected loss of clock reset events, all clock
monitors should be disabled before entering any low power
modes, including VLPR and VLPW.
22.2.2.5 Loss-of-lock (LOL) reset
The SCG module contains a loss-of-lock detector, to indicate a reset has been caused by a
loss of lock in the SCG PLL/FLL.
Reset
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
554 NXP Semiconductors