NXP Semiconductors KE1xF Series, Reference Manual, Page: 261 / 1483

12.3.19 Hardware Request Status Register (DMA_HRS)
The HRS register provides a bit map for the DMA channels, signaling the presence of a
hardware request for each channel. The hardware request status bits reflect the current
state of the register and qualified (via the ERQ fields) DMA request signals as seen by
the DMA’s arbitration logic. This view into the hardware request signals may be used for
debug purposes.
NOTE
These bits reflect the state of the request as seen by the
arbitration logic. Therefore, this status is affected by the ERQ
bits.
Address: 4000_8000h base + 34h offset = 4000_8034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
HRS15 HRS14 HRS13 HRS12 HRS11 HRS10
HRS9 HRS8 HRS7 HRS6 HRS5 HRS4 HRS3 HRS2 HRS1 HRS0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMA_HRS field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
15
HRS15
Hardware Request Status Channel 15
Table continues on the next page...
Chapter 12 Enhanced Direct Memory Access (eDMA)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 261