NXP Semiconductors KE1xF Series, Reference Manual, Page: 1460 / 1483

NOTE
In the preceding figures, the matching and arbitration timing
does not take into account the delay caused by the concurrent
memory access due to the CPU or other internal FlexCAN sub-
blocks.
50.5.8.6 Tx Arbitration start delay
The Tx Arbitration Start Delay (TASD) bit field in Control 2 register
(CAN_CTRL2[TASD]) is a variable that indicates the number of CAN bits used by
FlexCAN to delay the Tx Arbitration process start point from the first bit of CRC field of
the current frame. This variable can be written only in Freeze mode because it is blocked
by hardware in other modes.
The transmission performance is impacted by the ability of the CPU to reconfigure
Message Buffers (MBs) for transmission after the end of the internal Arbitration process,
where FlexCAN finds the winner MB for transmission (see
Arbitration process ). If the
Arbitration ends too early before the first bit of Intermission field, then there is a chance
that the CPU reconfigures some Tx MBs and the winner MB is no longer the best
candidate to be transmitted.
TASD is useful to optimize the transmission performance by defining the Arbitration
start point, as shown in the next figure, based on factors such as:
• The peripheral-to-oscillator clock ratio
• CAN bit timing variables that determine the CAN bit rate
• The number of Message Buffers (MBs) in use by the Matching and Arbitration
processes.
Intermission
start point
Arbitration
TASD countdown
S
O
F
Process
Arbitration
A
C
K
CRC
EOF
Arbitration window (25 CAN bits)
Figure 50-7. Optimal Tx Arbitration start point
Functional description
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
1460 NXP Semiconductors