NXP Semiconductors KE1xF Series, Reference Manual, Page: 1307 / 1483

Field Function
13-12
—
Reserved
11
M7
7-Bit Mode Select
This bit should only be changed when the transmitter and receiver are both disabled.
0 - Receiver and transmitter use 8-bit to 10-bit data characters.
1 - Receiver and transmitter use 7-bit data characters.
10-8
IDLECFG
Idle Configuration
Configures the number of idle characters that must be received before the IDLE flag is set.
000 - 1 idle character
001 - 2 idle characters
010 - 4 idle characters
011 - 8 idle characters
100 - 16 idle characters
101 - 32 idle characters
110 - 64 idle characters
111 - 128 idle characters
7
LOOPS
Loop Mode Select
When LOOPS is set, the RXD pin is disconnected from the LPUART and the transmitter output is
internally connected to the receiver input. The transmitter and the receiver must be enabled to use the
loop function.
0 - Normal operation - RXD and TXD use separate pins.
1 - Loop mode or single-wire mode where transmitter outputs are internally connected to receiver
input (see RSRC bit).
6
DOZEEN
Doze Enable
0 - LPUART is enabled in Doze mode.
1 - LPUART is disabled in Doze mode.
5
RSRC
Receiver Source Select
This field has no meaning or effect unless the LOOPS field is set. When LOOPS is set, the RSRC field
determines the source for the receiver shift register input.
0 - Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART
does not use the RXD pin.
1 - Single-wire LPUART mode where the TXD pin is connected to the transmitter output and
receiver input.
4
M
9-Bit or 8-Bit Mode Select
0 - Receiver and transmitter use 8-bit data characters.
1 - Receiver and transmitter use 9-bit data characters.
3
WAKE
Receiver Wakeup Method Select
Determines which condition wakes the LPUART when RWU=1:
• Address mark in the most significant bit position of a received data character, or
• An idle condition on the receive pin input signal.
0 - Configures RWU for idle-line wakeup.
1 - Configures RWU with address-mark wakeup.
2
ILT
Idle Line Type Select
Determines when the receiver starts counting logic 1s as idle character bits. The count begins either after
a valid start bit or after the stop bit. If the count begins after the start bit, then a string of logic 1s
preceding the stop bit can cause false recognition of an idle character. Beginning the count after the stop
bit avoids false idle character recognition, but requires properly synchronized transmissions.
Table continues on the next page...
Chapter 48 Low Power Universal Asynchronous Receiver/ Transmitter (LPUART)
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
NXP Semiconductors 1307