NXP Semiconductors KE1xF Series, Reference Manual, Page: 1138 / 1483

• 32-bit Periodic Counter: In this mode the counter will load and then decrement down
to zero. It will then set the timer interrupt flag and assert the output pre-trigger.
• Dual 16-bit Periodic Counter: In this mode, the counter will load and then the lower
16-bits will decrement down to zero, which will assert the output pre-trigger. The
upper 16-bits will then decrement down to zero, which will negate the output pre-
trigger and set the timer interrupt flag.
• 32-bit Trigger Accumulator: In this mode, the counter will load on the first trigger
rising edge and then decrement down to zero on each trigger rising edge. It will then
set the timer interrupt flag and assert the output pre-trigger.
• 32-bit Trigger Input Capture: In this mode, the counter will load with 0xFFFF_FFFF
and then decrement down to zero. If a trigger rising edge is detected, it will store the
inverse of the current counter value in the load value register, set the timer interrupt
flag and assert the output pre-trigger.
The timer operation is further controlled by Trigger Control bits (TSOT, TSOI, TROT)
which control the timer load, reload, start and restart of the timers.
NOTE
• The trigger output is asserted one Protocol Timer Clock
cycle later than pre-trigger output. The trigger output and
the pre-trigger output de-assert at the same time.
• The pre-trigger output is asserted for two clock cycles and
trigger output is asserted for one clock cycle (except in 16-
bit Periodic Counter mode where both pre-trigger and
trigger are asserted for many cycles depending on
TMR_VAL[31:16]).
42.5.3 Trigger Control for Timers
The TSOT, TROT, TSOI and TRG_SEL, TRG_SRC bits control how the trigger input
affects the timer operation. The TRG_SEL selects the input trigger for the channel from
all other channel's trigger outputs. The TRG_SRC further selects between the selected
internal trigger and the external trigger input to the channel.
The selected trigger affects the timer operation based on TROT, TSOI & TSOT bits. The
behavior due to these bits is as follows:
• If TSOI = 1, counter stops on TIF assertion. Requires trigger (if TSOT = 1) or T_EN
rising edge (if TSOT = 0), to reload and decrement. If TSOI = 0, counter does not
stop after timeout.
Functional description
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
1138 NXP Semiconductors